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authorShiraz Hashim <shiraz.hashim@st.com>2012-05-07 13:06:59 +0530
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-07-07 14:07:42 +0200
commit7c885a0e5532abcd6bc802d21a7858420e5c127b (patch)
tree9441156596340e8797fd535fc30a5cead8e7decf
parent8337aa5c0b22bc9e1d8ae9d7b2270735670233bd (diff)
SPEAr: explicitly select clk src for UART
UART in u-boot intends to run on 48MHz clock supplied by USB PLL. Explicitly select the intended clock source. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
-rw-r--r--arch/arm/cpu/arm926ejs/spear/cpu.c7
-rw-r--r--arch/arm/include/asm/arch-spear/spr_misc.h2
2 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
index 9e074bc9eb5..e299de3137a 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -30,7 +30,7 @@ int arch_cpu_init(void)
{
struct misc_regs *const misc_p =
(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
- u32 periph1_clken;
+ u32 periph1_clken, periph_clk_cfg;
periph1_clken = readl(&misc_p->periph1_clken);
@@ -42,6 +42,11 @@ int arch_cpu_init(void)
#if defined(CONFIG_PL011_SERIAL)
periph1_clken |= MISC_UART0ENB;
+
+ periph_clk_cfg = readl(&misc_p->periph_clk_cfg);
+ periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK;
+ periph_clk_cfg |= CONFIG_SPEAR_UART48M;
+ writel(periph_clk_cfg, &misc_p->periph_clk_cfg);
#endif
#if defined(CONFIG_DESIGNWARE_ETH)
periph1_clken |= MISC_ETHENB;
diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h
index b10c72607a5..384944d33e3 100644
--- a/arch/arm/include/asm/arch-spear/spr_misc.h
+++ b/arch/arm/include/asm/arch-spear/spr_misc.h
@@ -110,6 +110,8 @@ struct misc_regs {
/* PERIPH_CLK_CFG value */
#define MISC_GPT3SYNTH 0x00000400
#define MISC_GPT4SYNTH 0x00000800
+#define CONFIG_SPEAR_UART48M 0
+#define CONFIG_SPEAR_UARTCLKMSK (0x1 << 4)
/* PRSC_CLK_CFG value */
/*