diff options
author | Shiraz Hashim <shiraz.hashim@st.com> | 2012-05-07 13:06:53 +0530 |
---|---|---|
committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-07-07 14:07:41 +0200 |
commit | bda7f435a22c024959e831f089da19052cfff113 (patch) | |
tree | a80cccc68497cd8db674283e781a41ddc3019af8 | |
parent | 25b741a4efc280ab58e8a2d7b669de6d4ea4a7fb (diff) |
SPEAr: Enable dcache for fast file transfer
Enable data cache with 1:1 mapping of DDR to enable fast file
transfer over tty which was doing lot of copy.
This feature is enabled only for flashing operation i.e. when
CONFIG_SPEAR_USBTTY is enabled.
This has been tested on SPEAr320, SPEAr600 and SPEAr900 evaluation
boards.
Following figures show an estimate on the performance improvements. The
test setup was a Linux host (not Windows) and involved measurement of
only binary transfer time, through kermit. The flash erase and flash
copy time would be unaffected by these patches.
Another thing is this that the timings remained more or less same across
ARM9 and Cortex based devices, hence reporting only one of the cases.
Before Enhancements
===================
$ time ukermit.small -p /dev/ttyACM0 -f spear320_uImage.img
Downloading file: 100.00% completed(2014080/2014080 bytes)
real 0m41.228s
user 0m0.002s
sys 0m0.064s
After Enhancements
==================
$ time ukermit.large -p /dev/ttyACM0 -f spear320_uImage.img
Downloading file: 100.00% completed(2014080/2014080 bytes)
real 0m5.441s
user 0m0.001s
sys 0m0.001s
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
-rw-r--r-- | board/spear/common/spr_misc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c index 043c72a05d3..99a65959665 100644 --- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -76,6 +76,10 @@ int misc_init_r(void) setenv("stdin", "usbtty"); setenv("stdout", "usbtty"); setenv("stderr", "usbtty"); + +#ifndef CONFIG_SYS_NO_DCACHE + dcache_enable(); +#endif #endif return 0; } |