Fix SDRAM timing on Purple board

4 files changed, 77 insertions, 3 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 07417827165..c21c816634e 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,8 @@
 Changes since U-Boot 0.3.1:
 ======================================================================
 
+* Fix SDRAM timing on Purple board
+
 * Add support for CompactFlash on ATC board
   (includes support for Intel 82365 and compatible PC Card controllers,
   and Yenta-compatible PCI-to-CardBus controllers)
diff --git a/board/purple/memsetup.S b/board/purple/memsetup.S
index 55daf8a4301..9c983c9a556 100644
--- a/board/purple/memsetup.S
+++ b/board/purple/memsetup.S
@@ -26,10 +26,13 @@
 #include <version.h>
 #include <asm/regdef.h>
 
+#define MC_IOGP	0xBF800800
 
 	.globl	memsetup
 memsetup:
-
+	li	t0, MC_IOGP
+	li	t1, 0xf24
+	sw	t1, 0(t0)
 	j	ra
 	nop
 
diff --git a/board/purple/purple.c b/board/purple/purple.c
index 293cc560e19..dfd014b53b5 100644
--- a/board/purple/purple.c
+++ b/board/purple/purple.c
@@ -51,6 +51,69 @@ extern int	asc_serial_getc 	(void);
 extern int	asc_serial_tstc 	(void);
 extern void	asc_serial_setbrg 	(void);
 
+static void sdram_timing_init (ulong size)
+{
+	register uint pass;
+	register uint done;
+	register uint count;
+	register uint p0, p1, p2, p3, p4;
+	register uint addr;
+
+#define WRITE_MC_IOGP_1 *(uint *)0xbf800800 = (p1<<14)+(p2<<13)+(p4<<8)+(p0<<4)+p3;
+#define WRITE_MC_IOGP_2 *(uint *)0xbf800800 = (p1<<14)+(p2<<13)+((p4-16)<<8)+(p0<<4)+p3;
+
+	done = 0;
+	p0 = 2;
+	while (p0 < 4 && done == 0) {
+	    p1 = 0;
+	    while (p1 < 2 && done == 0) {
+		p2 = 0;
+		while (p2 < 2 && done == 0) {
+		    p3 = 0;
+		    while (p3 < 16 && done == 0) {
+			count = 0;
+			p4 = 0;
+			while (p4 < 32 && done == 0) {
+			    WRITE_MC_IOGP_1;
+
+			    for (addr = KSEG1 + 0x4000;
+				 addr < KSEG1ADDR (size);
+				 addr = addr + 4) {
+					*(uint *) addr = 0xaa55aa55;
+			    }
+
+			    pass = 1;
+
+			    for (addr = KSEG1 + 0x4000;
+				 addr < KSEG1ADDR (size) && pass == 1;
+				 addr = addr + 4) {
+					if (*(uint *) addr != 0xaa55aa55)
+						pass = 0;
+			    }
+
+			    if (pass == 1) {
+				count++;
+			    } else {
+				count = 0;
+			    }
+
+			    if (count == 32) {
+				WRITE_MC_IOGP_2;
+				done = 1;
+			    }
+			    p4++;
+			}
+			p3++;
+		    }
+		    p2++;
+		}
+		p1++;
+	    }
+	    p0++;
+	    if (p0 == 1)
+		p0++;
+	}
+}
 
 long int initdram(int board_type)
 {
@@ -64,6 +127,11 @@ long int initdram(int board_type)
 	int	rows	= (cfgpb0 & 0xF0) >> 4;
 	int	dw	= cfgdw & 0xF;
 	ulong	size	= (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB;
+	void (*  sdram_init) (ulong);
+
+	sdram_init = (void (*)(ulong)) KSEG0ADDR(&sdram_timing_init);
+
+	sdram_init(0x10000);
 
 	return size;
 }
diff --git a/include/configs/purple.h b/include/configs/purple.h
index 69f343cd9d9..7ffd3fd36f8 100644
--- a/include/configs/purple.h
+++ b/include/configs/purple.h
@@ -150,7 +150,8 @@
  * Temporary buffer for serial data until the real serial driver
  * is initialised (memtest will destroy this buffer)
  */
-#define CFG_SCONSOLE_ADDR     CFG_SDRAM_BASE
-#define CFG_SCONSOLE_SIZE     0x0002000
+#define CFG_SCONSOLE_ADDR     (CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET - \
+			       CFG_DCACHE_SIZE / 2)
+#define CFG_SCONSOLE_SIZE     (CFG_DCACHE_SIZE / 4)
 
 #endif	/* __CONFIG_H */