at91sam9263ek: add nor flash support

this will allow you to store use it for the env and to boot directly U-Boot from

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

6 files changed, 437 insertions, 9 deletions

diff --git a/Makefile b/Makefile
index eb58dfea0d0..a6f42319366 100644
--- a/Makefile
+++ b/Makefile
@@ -2754,6 +2754,8 @@ at91sam9261ek_config	:	unconfig
 	fi;
 	@$(MKCONFIG) -a at91sam9261ek arm arm926ejs at91sam9261ek atmel at91
 
+at91sam9263ek_norflash_config \
+at91sam9263ek_norflash_boot_config \
 at91sam9263ek_nandflash_config \
 at91sam9263ek_dataflash_config \
 at91sam9263ek_dataflash_cs0_config \
@@ -2762,10 +2764,17 @@ at91sam9263ek_config	:	unconfig
 	@if [ "$(findstring _nandflash,$@)" ] ; then \
 		echo "#define CONFIG_SYS_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
 		$(XECHO) "... with environment variable in NAND FLASH" ; \
+	elif [ "$(findstring norflash,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_NORFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in NOR FLASH" ; \
 	else \
 		echo "#define CONFIG_SYS_USE_DATAFLASH 1"	>>$(obj)include/config.h ; \
 		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
 	fi;
+	@if [ "$(findstring norflash_boot,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_BOOT_NORFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... and boot from NOR FLASH" ; \
+	fi;
 	@$(MKCONFIG) -a at91sam9263ek arm arm926ejs at91sam9263ek atmel at91
 
 at91sam9rlek_nandflash_config \
diff --git a/board/atmel/at91sam9263ek/Makefile b/board/atmel/at91sam9263ek/Makefile
index 013ed215f9f..19a354b6e1c 100644
--- a/board/atmel/at91sam9263ek/Makefile
+++ b/board/atmel/at91sam9263ek/Makefile
@@ -32,10 +32,13 @@ LIB	= $(obj)lib$(BOARD).a
 COBJS-y += at91sam9263ek.o
 COBJS-y += led.o
 COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS-y += lowlevel_init.o
+endif
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index 57d5c953f77..660c4734454 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -196,9 +196,16 @@ static void at91sam9263ek_lcd_hw_init(void)
 #include <nand.h>
 #include <version.h>
 
+#ifndef CONFIG_SYS_NO_FLASH
+extern flash_info_t flash_info[];
+#endif
+
 void lcd_show_board_info(void)
 {
 	ulong dram_size, nand_size;
+#ifndef CONFIG_SYS_NO_FLASH
+	ulong flash_size;
+#endif
 	int i;
 	char temp[32];
 
@@ -215,9 +222,19 @@ void lcd_show_board_info(void)
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 		nand_size += nand_info[i].size;
-	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
+#ifndef CONFIG_SYS_NO_FLASH
+	flash_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+		flash_size += flash_info[i].size;
+#endif
+	lcd_printf ("  %ld MB SDRAM, %ld MB NAND",
 		dram_size >> 20,
 		nand_size >> 20 );
+#ifndef CONFIG_SYS_NO_FLASH
+	lcd_printf (",\n  %ld MB NOR",
+		flash_size >> 20);
+#endif
+	lcd_puts ("\n");
 }
 #endif /* CONFIG_LCD_INFO */
 #endif
diff --git a/board/atmel/at91sam9263ek/lowlevel_init.S b/board/atmel/at91sam9263ek/lowlevel_init.S
new file mode 100644
index 00000000000..3a957776df9
--- /dev/null
+++ b/board/atmel/at91sam9263ek/lowlevel_init.S
@@ -0,0 +1,264 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
+ * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_wdt.h>
+#include <asm/arch/at91sam9_sdramc.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91sam9263_matrix.h>
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl lowlevel_init
+.type lowlevel_init,function
+lowlevel_init:
+
+	mov	r5, pc		/* r5 = POS1 + 4 current */
+POS1:
+	ldr	r0, =POS1	/* r0 = POS1 compile */
+	ldr	r2, _TEXT_BASE
+	sub	r0, r0, r2	/* r0 = POS1-_TEXT_BASE (POS1 relative) */
+	sub	r5, r5, r0	/* r0 = TEXT_BASE-1 */
+	sub	r5, r5, #4	/* r1 = text base - current */
+
+	/* memory control configuration 1 */
+	ldr	r0, =SMRDATA
+	ldr	r2, =SMRDATA1
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	sub	r2, r2, r1
+	add	r0, r0, r5
+	add	r2, r2, r5
+0:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	0b
+
+/* ----------------------------------------------------------------------------
+ * PMC Init Step 1.
+ * ----------------------------------------------------------------------------
+ * - Check if the PLL is already initialized
+ * ----------------------------------------------------------------------------
+ */
+	ldr	r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
+	ldr	r0, [r1]
+	and	r0, r0, #3
+	cmp	r0, #0
+	bne	PLL_setup_end
+
+/* ---------------------------------------------------------------------------
+ * - Enable the Main Oscillator
+ * ---------------------------------------------------------------------------
+ */
+	ldr	r1, =(AT91_BASE_SYS + AT91_CKGR_MOR)
+	ldr	r2, =(AT91_BASE_SYS + AT91_PMC_SR)
+	ldr	r0, =CONFIG_SYS_MOR_VAL
+	str	r0, [r1]	/* Enable main oscillator, OSCOUNT = 0xFF */
+
+	/* Reading the PMC Status to detect when the Main Oscillator is enabled */
+	mov	r4, #AT91_PMC_MOSCS
+MOSCS_Loop:
+	ldr	r3, [r2]
+	and	r3, r4, r3
+	cmp	r3, #AT91_PMC_MOSCS
+	bne	MOSCS_Loop
+
+/* ----------------------------------------------------------------------------
+ * PMC Init Step 2.
+ * ----------------------------------------------------------------------------
+ * Setup PLLA
+ * ----------------------------------------------------------------------------
+ */
+	ldr	r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR)
+	ldr	r0, =CONFIG_SYS_PLLAR_VAL
+	str	r0, [r1]
+
+	/* Reading the PMC Status register to detect when the PLLA is locked */
+	mov	r4, #AT91_PMC_LOCKA
+MOSCS_Loop1:
+	ldr	r3, [r2]
+	and	r3, r4, r3
+	cmp	r3, #AT91_PMC_LOCKA
+	bne	MOSCS_Loop1
+
+/* ----------------------------------------------------------------------------
+ * PMC Init Step 3.
+ * ----------------------------------------------------------------------------
+ * - Switch on the Main Oscillator 16.367 MHz
+ * ----------------------------------------------------------------------------
+ */
+	ldr	r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
+
+	/* -Master Clock Controller register PMC_MCKR */
+	ldr	r0, =CONFIG_SYS_MCKR1_VAL
+	str	r0, [r1]
+
+	/* Reading the PMC Status to detect when the Master clock is ready */
+	mov	r4, #AT91_PMC_MCKRDY
+MCKRDY_Loop:
+	ldr	r3, [r2]
+	and	r3, r4, r3
+	cmp	r3, #AT91_PMC_MCKRDY
+	bne	MCKRDY_Loop
+
+	ldr	r0, =CONFIG_SYS_MCKR2_VAL
+	str	r0, [r1]
+
+	/* Reading the PMC Status to detect when the Master clock is ready */
+	mov	r4, #AT91_PMC_MCKRDY
+MCKRDY_Loop1:
+	ldr	r3, [r2]
+	and	r3, r4, r3
+	cmp	r3, #AT91_PMC_MCKRDY
+	bne	MCKRDY_Loop1
+
+PLL_setup_end:
+
+/* ----------------------------------------------------------------------------
+ * - memory control configuration 2
+ * ----------------------------------------------------------------------------
+ */
+	ldr	r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR)
+	ldr	r1, [r0]
+	cmp	r1, #0
+	bne	SDRAM_setup_end
+
+	ldr	r0, =SMRDATA1
+	ldr	r2, =SMRDATA2
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	sub	r2, r2, r1
+	add	r0, r0, r5
+	add	r2, r2, r5
+
+2:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	2b
+
+SDRAM_setup_end:
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+
+SMRDATA:
+	.word (AT91_BASE_SYS + AT91_WDT_MR)
+	.word CONFIG_SYS_WDTC_WDMR_VAL
+
+	.word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR)
+	.word CONFIG_SYS_PIOD_PDR_VAL1
+	.word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR)
+	.word CONFIG_SYS_PIOD_PPUDR_VAL
+	.word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
+	.word CONFIG_SYS_PIOD_PPUDR_VAL
+
+	.word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA)
+	.word CONFIG_SYS_MATRIX_EBI0CSA_VAL
+
+	/* flash */
+	.word (AT91_BASE_SYS + AT91_SMC_MODE(0))
+	.word CONFIG_SYS_SMC0_MODE0_VAL
+
+	.word (AT91_BASE_SYS + AT91_SMC_CYCLE(0))
+	.word CONFIG_SYS_SMC0_CYCLE0_VAL
+
+	.word (AT91_BASE_SYS + AT91_SMC_PULSE(0))
+	.word CONFIG_SYS_SMC0_PULSE0_VAL
+
+	.word (AT91_BASE_SYS + AT91_SMC_SETUP(0))
+	.word CONFIG_SYS_SMC0_SETUP0_VAL
+
+SMRDATA1:
+	.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
+	.word CONFIG_SYS_SDRC_MR_VAL1
+	.word (AT91_BASE_SYS + AT91_SDRAMC_TR)
+	.word CONFIG_SYS_SDRC_TR_VAL1
+	.word (AT91_BASE_SYS + AT91_SDRAMC_CR)
+	.word CONFIG_SYS_SDRC_CR_VAL
+	.word (AT91_BASE_SYS + AT91_SDRAMC_MDR)
+	.word CONFIG_SYS_SDRC_MDR_VAL
+	.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
+	.word CONFIG_SYS_SDRC_MR_VAL2
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL1
+	.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
+	.word CONFIG_SYS_SDRC_MR_VAL3
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL2
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL3
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL4
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL5
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL6
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL7
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL8
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL9
+	.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
+	.word CONFIG_SYS_SDRC_MR_VAL4
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL10
+	.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
+	.word CONFIG_SYS_SDRC_MR_VAL5
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL11
+	.word (AT91_BASE_SYS + AT91_SDRAMC_TR)
+	.word CONFIG_SYS_SDRC_TR_VAL2
+	.word AT91_SDRAM_BASE
+	.word CONFIG_SYS_SDRAM_VAL12
+	/* User reset enable*/
+	.word (AT91_BASE_SYS + AT91_RSTC_MR)
+	.word CONFIG_SYS_RSTC_RMR_VAL
+#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
+	/* MATRIX_MCFG - REMAP all masters */
+	.word (AT91_BASE_SYS + AT91_MATRIX_MCFG0)
+	.word 0x1FF
+#endif
+
+SMRDATA2:
+	.word 0
diff --git a/doc/README.at91 b/doc/README.at91
index 9b4eae6e143..4a2c56bd9ed 100644
--- a/doc/README.at91
+++ b/doc/README.at91
@@ -62,11 +62,16 @@ Environment variables
 	U-Boot environment variables can be stored at different places:
 		- Dataflash on SPI chip select 0 (dataflash card)
 		- Nand flash.
+		- Nor falsh (not populate by default)
 
 	You can choose your storage location at config step (here for at91sam9260ek) :
 		make at91sam9263ek_config		- use data flash (spi cs0) (default)
 		make at91sam9263ek_nandflash_config	- use nand flash
 		make at91sam9263ek_dataflash_cs0_config	- use data flash (spi cs0)
+		make at91sam9263ek_norflash_config	- use nor falsh
+
+	You can choose to boot directly from U-Boot at config step
+		make at91sam9263ek_norflash_boot_config	- boot from nor falsh
 
 
 ------------------------------------------------------------------------------
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index c212d11d0d2..00f3114fb5d 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -41,8 +41,10 @@
 #define CONFIG_SETUP_MEMORY_TAGS 1
 #define CONFIG_INITRD_TAG	1
 
+#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SKIP_RELOCATE_UBOOT
+#endif
 
 /*
  * Hardware drivers
@@ -113,15 +115,143 @@
 #define DATAFLASH_TCHS			(0x1 << 24)
 
 /* NOR flash, if populated */
-#if 1
-#define CONFIG_SYS_NO_FLASH			1
-#else
+#ifdef CONFIG_SYS_USE_NORFLASH
 #define CONFIG_SYS_FLASH_CFI			1
-#define CONFIG_FLASH_CFI_DRIVER		1
-#define PHYS_FLASH_1			0x10000000
+#define CONFIG_FLASH_CFI_DRIVER			1
+#define PHYS_FLASH_1				0x10000000
 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
 #define CONFIG_SYS_MAX_FLASH_SECT		256
 #define CONFIG_SYS_MAX_FLASH_BANKS		1
+
+#define CONFIG_SYS_MONITOR_SEC	1:0-3
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN	(256 << 10)
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x007FE000)
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
+
+/* Address and size of Primary Environment Sector */
+#define CONFIG_ENV_SIZE		0x2000
+
+#define xstr(s)   str(s)
+#define str(s)	#s
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"monitor_base=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+	"update=" \
+		"protect off ${monitor_base} +${filesize};" \
+		"erase ${monitor_base} +${filesize};" \
+		"cp.b ${load_addr} ${monitor_base} ${filesize};" \
+		"protect on ${monitor_base} +${filesize}\0"
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define MASTER_PLL_MUL		171
+#define MASTER_PLL_DIV		14
+
+/* clocks */
+#define CONFIG_SYS_MOR_VAL						\
+		(AT91_PMC_MOSCEN |					\
+		 (255 << 8))		/* Main Oscillator Start-up Time */
+#define CONFIG_SYS_PLLAR_VAL						\
+		(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
+		 AT91_PMC_OUT |						\
+		 AT91_PMC_PLLCOUNT |	/* PLL Counter */		\
+		 (2 << 28) |		/* PLL Clock Frequency Range */	\
+		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR1_VAL		\
+		(AT91_PMC_CSS_SLOW |	\
+		 AT91_PMC_PRES_1 |	\
+		 AT91SAM9_PMC_MDIV_2 |	\
+		 AT91_PMC_PDIV_1)
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR2_VAL		\
+		(AT91_PMC_CSS_PLLA |	\
+		 AT91_PMC_PRES_1 |	\
+		 AT91SAM9_PMC_MDIV_2 |	\
+		 AT91_PMC_PDIV_1)
+
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
+/* no pull-up for D[31:16] */
+#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
+/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+#define CONFIG_SYS_MATRIX_EBI0CSA_VAL					\
+	(AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |	\
+	 AT91_MATRIX_EBI0_CS1A_SDRAMC)
+
+/* SDRAM */
+/* SDRAMC_MR Mode register */
+#define CONFIG_SYS_SDRC_MR_VAL1		0
+/* SDRAMC_TR - Refresh Timer register */
+#define CONFIG_SYS_SDRC_TR_VAL1		0x13C
+/* SDRAMC_CR - Configuration register*/
+#define CONFIG_SYS_SDRC_CR_VAL							\
+		(AT91_SDRAMC_NC_9 |						\
+		 AT91_SDRAMC_NR_13 |						\
+		 AT91_SDRAMC_NB_4 |						\
+		 AT91_SDRAMC_CAS_3 |						\
+		 AT91_SDRAMC_DBW_32 |						\
+		 (1 <<  8) |		/* Write Recovery Delay */		\
+		 (7 << 12) |		/* Row Cycle Delay */			\
+		 (2 << 16) |		/* Row Precharge Delay */		\
+		 (2 << 20) |		/* Row to Column Delay */		\
+		 (5 << 24) |		/* Active to Precharge Delay */		\
+		 (1 << 28))		/* Exit Self Refresh to Active Delay */
+
+/* Memory Device Register -> SDRAM */
+#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
+#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
+#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
+#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
+#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
+
+/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
+#define CONFIG_SYS_SMC0_SETUP0_VAL					\
+		(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |	\
+		 AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL					\
+		(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |	\
+		 AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+		(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
+#define CONFIG_SYS_SMC0_MODE0_VAL				\
+		(AT91_SMC_READMODE | AT91_SMC_WRITEMODE |	\
+		 AT91_SMC_DBW_16 |				\
+		 AT91_SMC_TDFMODE |				\
+		 AT91_SMC_TDF_(6))
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL			\
+		(AT91_RSTC_KEY |		\
+		AT91_RSTC_PROCRST |		\
+		AT91_RSTC_RSTTYP_WAKEUP |	\
+		AT91_RSTC_RSTTYP_WATCHDOG)
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL				\
+		(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |	\
+		 AT91_WDT_WDV |					\
+		 AT91_WDT_WDDIS |				\
+		 AT91_WDT_WDD)
+#endif
+
+#else
+#define CONFIG_SYS_NO_FLASH			1
 #endif
 
 /* NAND flash */
@@ -175,7 +305,7 @@
 				"mtdparts=at91_nand:-(root) "\
 				"rw rootfstype=jffs2"
 
-#else /* CONFIG_SYS_USE_NANDFLASH */
+#elif CONFIG_SYS_USE_NANDFLASH
 
 /* bootstrap + u-boot + env + linux in nandflash */
 #define CONFIG_ENV_IS_IN_NAND	1