diff options
| author | Robby Cai <R63905@freescale.com> | 2012-08-23 15:47:20 +0800 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2012-09-12 11:05:55 -0400 |
| commit | 912353f4a6dcbffdb6ac5d07e158d7b57daaf785 (patch) | |
| tree | 0cd6df2b89207a1173bd76e61929f2d23f1239f6 | |
| parent | 293ab0eeecedb938b48a438b25f25e941dabcd04 (diff) | |
ENGR00221135: imx6x: clear PowerDown Enable bit of WDOG1_WMCR
From IC spec:
| -rw-r--r-- | board/freescale/mx6sl_arm2/mx6sl_arm2.c | 5 | ||||
| -rw-r--r-- | board/freescale/mx6sl_evk/mx6sl_evk.c | 5 | ||||
| -rw-r--r-- | include/imx_wdog.h | 39 |
3 files changed, 45 insertions, 4 deletions
diff --git a/board/freescale/mx6sl_arm2/mx6sl_arm2.c b/board/freescale/mx6sl_arm2/mx6sl_arm2.c index f14b2b607c..8abfd4e652 100644 --- a/board/freescale/mx6sl_arm2/mx6sl_arm2.c +++ b/board/freescale/mx6sl_arm2/mx6sl_arm2.c @@ -31,6 +31,7 @@ #include <asm/arch/iomux-v3.h> #include <asm/arch/regs-anadig.h> #include <asm/errno.h> +#include <imx_wdog.h> #ifdef CONFIG_MXC_FEC #include <miiphy.h> #endif @@ -1004,8 +1005,6 @@ void setup_pmic_voltages(void) val |= BF_ANADIG_REG_CORE_REG1_TRG(0x1f); REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val); - /*clear PowerDown Enable bit of WDOG1_WMCR*/ - writew(0, WDOG1_BASE_ADDR + 0x08); printf("hw_anadig_reg_core=%x\n", REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE)); #endif @@ -1025,6 +1024,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + wdog_preconfig(WDOG1_BASE_ADDR); + setup_uart(); #ifdef CONFIG_MXC_FEC diff --git a/board/freescale/mx6sl_evk/mx6sl_evk.c b/board/freescale/mx6sl_evk/mx6sl_evk.c index 63705ea94e..85c3b6142d 100644 --- a/board/freescale/mx6sl_evk/mx6sl_evk.c +++ b/board/freescale/mx6sl_evk/mx6sl_evk.c @@ -31,6 +31,7 @@ #include <asm/arch/iomux-v3.h> #include <asm/arch/regs-anadig.h> #include <asm/errno.h> +#include <imx_wdog.h> #ifdef CONFIG_MXC_FEC #include <miiphy.h> #endif @@ -973,8 +974,6 @@ void setup_pmic_voltages(void) val |= BF_ANADIG_REG_CORE_REG1_TRG(0x1f); REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val); - /*clear PowerDown Enable bit of WDOG1_WMCR */ - writew(0, WDOG1_BASE_ADDR + 0x08); printf("hw_anadig_reg_core=%x\n", REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE)); #endif @@ -994,6 +993,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + wdog_preconfig(WDOG1_BASE_ADDR); + setup_uart(); #ifdef CONFIG_MXC_FEC diff --git a/include/imx_wdog.h b/include/imx_wdog.h new file mode 100644 index 0000000000..40920f7774 --- /dev/null +++ b/include/imx_wdog.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef _IMX_WDOG_H +#define _IMX_WDOG_H + +#include <asm/io.h> + +#define WDOGx_WMCR 0x8 +static inline void wdog_preconfig(int base_addr) +{ + /* + * From IC spec: + * The Power down Counter inside WDOG-1 will be enabled out of reset. + * This counter has a fixed time-out value of 16 seconds, after which + * it will drive the WDOG-1 signal low. + * + * To prevent this, the software must disable this counter by clearing + * the PDE bit of Watchdog Miscellaneous Control Register (WDOG_WMCR). + */ + writew(0, base_addr + WDOGx_WMCR); +} + +#endif |