diff options
| author | York Sun <yorksun@freescale.com> | 2013-06-25 11:37:41 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-09 12:41:38 -0700 |
| commit | cb93071bb6da21d17dd7d7d414a389b380f959b2 (patch) | |
| tree | ef8cc19e0c01b00baeda237802d4b6b383d5e5f7 /README | |
| parent | 7adefb55adf3e55f3788c3b9682ba91d29da2595 (diff) | |
mpc85xx: Base emulator support
Prepare for emulator support for mpc85xx parts.
Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers.
These two registers improve stability but not supported by emulator.
Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -413,6 +413,10 @@ The following options need to be configured: CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT This value denotes start offset of DSP CCSR space. + CONFIG_SYS_FSL_DDR_EMU + Specify emulator support for DDR. Some DDR features such as + deskew training are not available. + - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN |