diff options
| author | Tom Rini <trini@ti.com> | 2014-08-29 11:06:51 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-08-29 11:06:51 -0400 |
| commit | 5a1095a830299aef8dd32495e505e92ab1749e89 (patch) | |
| tree | 9383de2534455119d51200bc87766a330591df27 /README | |
| parent | 6af857c50df4e62ec08e51ad73c96f63f1480386 (diff) | |
| parent | d145878d59c80a44d8c6e6d606b898ab87d205ee (diff) | |
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Diffstat (limited to 'README')
| -rw-r--r-- | README | 15 |
1 files changed, 15 insertions, 0 deletions
@@ -1378,6 +1378,10 @@ The following options need to be configured: CONFIG_SH_ETHER_CACHE_WRITEBACK If this option is set, the driver enables cache flush. +- PWM Support: + CONFIG_PWM_IMX + Support for PWM modul on the imx6. + - TPM Support: CONFIG_TPM Support TPM devices. @@ -2949,6 +2953,17 @@ CBFS (Coreboot Filesystem) support memories can be connected with a given cs line. currently Xilinx Zynq qspi support these type of connections. + CONFIG_SYS_SPI_ST_ENABLE_WP_PIN + enable the W#/Vpp signal to disable writing to the status + register on ST MICRON flashes like the N25Q128. + The status register write enable/disable bit, combined with + the W#/VPP signal provides hardware data protection for the + device as follows: When the enable/disable bit is set to 1, + and the W#/VPP signal is driven LOW, the status register + nonvolatile bits become read-only and the WRITE STATUS REGISTER + operation will not execute. The only way to exit this + hardware-protected mode is to drive W#/VPP HIGH. + - SystemACE Support: CONFIG_SYSTEMACE |