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authorDaniel Schwierzeck <daniel.schwierzeck@googlemail.com>2012-04-02 02:57:56 +0000
committerMarek Vasut <marex@denx.de>2012-04-02 15:54:53 +0200
commit6cb461b4f1531dbae5c0bae857f649b7943114ec (patch)
treebd8df91ecc1ebbd2d2cef76bfd1940b74e9920ee /README
parent979cfeaf36bf8719d4a1a98f1e8a3e16ef3d1fba (diff)
MIPS: fix endianess handling
Make endianess of target CPU configurable. Use the new config option for dbau1550_el and pb1000 boards. Adapt linking of standalone applications to pass through endianess options to LD. Build tested with: - ELDK 4 mips_4KC- and mips4KCle - Sourcery CodeBench Lite 2011.03-93 With this patch all 26 MIPS boards can be compiled now in one step by running "MAKEALL -a mips". Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Diffstat (limited to 'README')
-rw-r--r--README6
1 files changed, 6 insertions, 0 deletions
diff --git a/README b/README
index c98afa74b18..9702067174e 100644
--- a/README
+++ b/README
@@ -374,6 +374,12 @@ The following options need to be configured:
Defines the string to utilize when trying to match PCIe device
tree nodes for the given platform.
+- Generic CPU options:
+ CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
+
+ Defines the endianess of the CPU. Implementation of those
+ values is arch specific.
+
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO