Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'

3 files changed, 45 insertions, 7 deletions

diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index 168f525ec7c..c6f3b029a16 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -82,7 +82,7 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
 		{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
 	},
 	/*
-	 * T30: 1.4 GHz
+	 * T30: 600 MHz
 	 *
 	 * Register   Field  Bits   Width
 	 * ------------------------------
@@ -92,10 +92,10 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
 	 * PLLX_MISC  cpcon  11: 8    4
 	 */
 	{
-		{ .n = 862, .m =  8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
-		{ .n = 583, .m =  8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */
-		{ .n = 700, .m =  6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
-		{ .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
+		{ .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
+		{ .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
+		{ .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
+		{ .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
 	},
 	/*
 	 * T114: 700 MHz
diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c
index a80648389c7..9003902e3ff 100644
--- a/arch/arm/cpu/arm720t/tegra30/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra30/cpu.c
@@ -41,10 +41,18 @@ void tegra_i2c_ll_write_data(uint data, uint config)
 	writel(config, &reg->cnfg);
 }
 
+#define TPS62366A_I2C_ADDR		0xC0
+#define TPS62366A_SET1_REG		0x01
+#define TPS62366A_SET1_DATA		(0x4600 | TPS62366A_SET1_REG)
+
+#define TPS62361B_I2C_ADDR		0xC0
+#define TPS62361B_SET3_REG		0x03
+#define TPS62361B_SET3_DATA		(0x4600 | TPS62361B_SET3_REG)
+
 #define TPS65911_I2C_ADDR		0x5A
 #define TPS65911_VDDCTRL_OP_REG		0x28
 #define TPS65911_VDDCTRL_SR_REG		0x27
-#define TPS65911_VDDCTRL_OP_DATA	(0x2300 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_OP_DATA	(0x2400 | TPS65911_VDDCTRL_OP_REG)
 #define TPS65911_VDDCTRL_SR_DATA	(0x0100 | TPS65911_VDDCTRL_SR_REG)
 #define I2C_SEND_2_BYTES		0x0A02
 
@@ -58,9 +66,20 @@ static void enable_cpu_power_rail(void)
 	reg |= CPUPWRREQ_OE;
 	writel(reg, &pmc->pmc_cntrl);
 
+	/* Set VDD_CORE to 1.200V. */
+#ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
+	tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES);
+#endif
+#ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
+	tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES);
+#endif
+	udelay(1000);
+
 	/*
 	 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
-	 * First set VDD to 1.4V, then enable the VDD regulator.
+	 * First set VDD to 1.0125V, then enable the VDD regulator.
 	 */
 	tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
 	tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/cpu/tegra-common/pinmux-common.c
index d62618cd0f6..6e3ab0c14ca 100644
--- a/arch/arm/cpu/tegra-common/pinmux-common.c
+++ b/arch/arm/cpu/tegra-common/pinmux-common.c
@@ -86,12 +86,31 @@
 #define IO_RESET_SHIFT	8
 #define RCV_SEL_SHIFT	9
 
+#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
+/* This register/field only exists on Tegra114 and later */
+#define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
+#define CLAMP_INPUTS_WHEN_TRISTATED 1
+
+void pinmux_set_tristate_input_clamping(void)
+{
+	u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
+	u32 val;
+
+	val = readl(reg);
+	val |= CLAMP_INPUTS_WHEN_TRISTATED;
+	writel(val, reg);
+}
+#endif
+
 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
 {
 	u32 *reg = MUX_REG(pin);
 	int i, mux = -1;
 	u32 val;
 
+	if (func == PMUX_FUNC_DEFAULT)
+		return;
+
 	/* Error check on pin and func */
 	assert(pmux_pingrp_isvalid(pin));
 	assert(pmux_func_isvalid(func));