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authorTim Harvey <tharvey@gateworks.com>2022-04-13 11:31:09 -0700
committerStefano Babic <sbabic@denx.de>2022-04-21 12:44:24 +0200
commit2395625209cc315fce9502b947a510512e746797 (patch)
tree6958c3c23e4777e72ccef0577871426f6639dad9 /arch/arm/dts/imx8mp-venice-u-boot.dtsi
parent93de85c9d76a45c3e1f9efc8894d356c9898255f (diff)
board: gateworks: venice: add imx8mp-venice-gw740x support
The GW74xx is based on the i.MX 8M Plus SoC featuring: - LPDDR4 DRAM - eMMC FLASH - Gateworks System Controller - PCIe Gen 3.0 switch (build option) - USB 3.0 HUB - USB Type-C front panel connector - GPS - 3-axis accelerometer - CAN bus - 6x GbE RJ45 front-panel jacks - 1x IMX8M FEC RGMII GbE (with Passive PoE) - 5x IMX8M EQOS RGMII 6 port GbE Switch (1x with 802.3af class 5 Active PoE) - RS232/RS485/RS422 serial transceiver - MIPI header (DSI/CSI/GPIO/PWM/I2S) - DigI/O header (UART/GPIO/I2C/ADC) - 802.11ac WiFi - Bluetooth BLE - 3x MiniPCIe sockets with PCI/USB - 1x M.2 Socket with USB2.0, PCIe, and dual-SIM - PMIC - Wide range DC input supply (8V to 60V DC) Do the following to add support for this and future imx8mp-venice boards: - add dts - add DRAM config - add PMIC config - add IMX8MP support in spl.c and venice.c Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Diffstat (limited to 'arch/arm/dts/imx8mp-venice-u-boot.dtsi')
-rw-r--r--arch/arm/dts/imx8mp-venice-u-boot.dtsi74
1 files changed, 74 insertions, 0 deletions
diff --git a/arch/arm/dts/imx8mp-venice-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-u-boot.dtsi
new file mode 100644
index 0000000000..37f3edc981
--- /dev/null
+++ b/arch/arm/dts/imx8mp-venice-u-boot.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Gateworks Corporation
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&gsc {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c2 {
+ u-boot,dm-spl;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};