diff options
| author | Lokesh Vutla <lokeshvutla@ti.com> | 2019-06-13 10:29:53 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-07-26 21:49:28 -0400 |
| commit | eeb2e8b6ebf9d7529976e4a4fb0bb4454c907de6 (patch) | |
| tree | 662a860826698c8d50c32ac9c3c71318040d12a0 /arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | |
| parent | 382f1dda977e9f5a1fba23cb6b7fed136c767a4c (diff) | |
arm: dts: ti: Add Support for J721E SoC
Add initial SoC definition for J721E SoC.
Kernel dts posted here:
https://lore.kernel.org/lkml/20190522161921.20750-1-nm@ti.com/
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/dts/k3-j721e-mcu-wakeup.dtsi')
| -rw-r--r-- | arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi new file mode 100644 index 00000000000..1175fa9a503 --- /dev/null +++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals + * + * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +&cbass_mcu_wakeup { + dmsc: dmsc@44083000 { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + + mbox-names = "rx", "tx"; + + mboxes= <&secure_proxy_main 11>, + <&secure_proxy_main 13>; + + reg-names = "debug_messages"; + reg = <0x00 0x44083000 0x0 0x1000>; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + }; + + k3_clks: clocks { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + ti,scan-clocks-from-dt; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + }; + + wkup_pmx0: pinmux@4301c000 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c000 0x00 0x178>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_uart0: serial@42300000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x42300000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <48000000>; + current-speed = <115200>; + power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 287 0>; + clock-names = "fclk"; + }; + + mcu_uart0: serial@40a00000 { + compatible = "ti,j721e-uart", "ti,am654-uart"; + reg = <0x00 0x40a00000 0x00 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <96000000>; + current-speed = <115200>; + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 149 0>; + clock-names = "fclk"; + }; +}; |