summaryrefslogtreecommitdiff
path: root/arch/arm/dts/r8a77970-eagle.dts
diff options
context:
space:
mode:
authorMarek Vasut <marek.vasut+renesas@gmail.com>2017-10-09 21:08:10 +0200
committerMarek Vasut <marex@denx.de>2017-12-09 13:36:27 +0100
commitd21f08ba818138ed3f81ab755021bdae28c17690 (patch)
tree1f408f844066544019a3174161c175892d433948 /arch/arm/dts/r8a77970-eagle.dts
parent9e4a63736e50e99134e04321e7e6bdd2e5d7d694 (diff)
ARM: rmobile: Add R8A77970 V3M Eagle board
Add bits to support yet another board, the R8A77970 V3M Eagle. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'arch/arm/dts/r8a77970-eagle.dts')
-rw-r--r--arch/arm/dts/r8a77970-eagle.dts87
1 files changed, 87 insertions, 0 deletions
diff --git a/arch/arm/dts/r8a77970-eagle.dts b/arch/arm/dts/r8a77970-eagle.dts
new file mode 100644
index 0000000000..71a379f9e2
--- /dev/null
+++ b/arch/arm/dts/r8a77970-eagle.dts
@@ -0,0 +1,87 @@
+/*
+ * Device Tree Source for the Eagle board
+ *
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a77970.dtsi"
+
+/ {
+ model = "Renesas Eagle board based on r8a77970";
+ compatible = "renesas,eagle", "renesas,r8a77970";
+
+ aliases {
+ serial0 = &scif0;
+ ethernet0 = &avb;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x38000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
+};
+
+&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk_b";
+ function = "scif_clk";
+ };
+
+ avb_pins: avb {
+ groups = "avb0_mdc";
+ function = "avb0";
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+ status = "okay";
+};
+
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+ renesas,no-ether-link;
+ phy-handle = <&phy0>;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ };
+};