diff options
| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2018-05-18 22:05:25 +0800 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-05-18 10:30:48 +0200 |
| commit | 5fb033a3368d78cc1d2460cc4db5880398513b26 (patch) | |
| tree | 0038d41b489c1f31ece1464f6dad29b0aeafa77c /arch/arm/dts/socfpga_stratix10.dtsi | |
| parent | 73175d04a9351857e4314cbe4cd64cbb9f27c69e (diff) | |
arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switch
Preparation for Stratix 10 enablement. In ARM64, L2 cache controller is
accessed through processor registers. So, add CONFIG_SYS_L2_PL310 switch
conditional build in order this file can by shared across other SOCFPGAs.
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch/arm/dts/socfpga_stratix10.dtsi')
0 files changed, 0 insertions, 0 deletions