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authorAlbert ARIBAUD \(3ADEV\) <albert.aribaud@3adev.fr>2015-03-31 11:40:46 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2015-04-10 14:23:09 +0200
commit606f7047603422746d112e41937649d44f311af4 (patch)
treece2cabc328db2721e3ae3204f16e2cb637b4ba79 /arch/arm
parent5e862b95399e6e5ea7748ee29a38756685d622fd (diff)
lpc32xx: add GPIO support
This driver only supports Driver Model, not legacy model. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/arm926ejs/lpc32xx/devices.c5
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/gpio.h43
2 files changed, 48 insertions, 0 deletions
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 81b53eaa6d..a407098eda 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -9,6 +9,7 @@
#include <asm/arch/clk.h>
#include <asm/arch/uart.h>
#include <asm/io.h>
+#include <dm.h>
static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
@@ -61,3 +62,7 @@ void lpc32xx_i2c_init(unsigned int devnum)
ctrl |= CLK_I2C2_ENABLE;
writel(ctrl, &clk->i2cclk_ctrl);
}
+
+U_BOOT_DEVICE(lpc32xx_gpios) = {
+ .name = "gpio_lpc32xx"
+};
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h b/arch/arm/include/asm/arch-lpc32xx/gpio.h
new file mode 100644
index 0000000000..3bd94e31a5
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/gpio.h
@@ -0,0 +1,43 @@
+/*
+ * LPC32xx GPIO interface
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/**
+ * GPIO Register map for LPC32xx
+ */
+
+struct gpio_regs {
+ u32 p3_inp_state;
+ u32 p3_outp_set;
+ u32 p3_outp_clr;
+ u32 p3_outp_state;
+ /* Watch out! the following are shared between p2 and p3 */
+ u32 p2_p3_dir_set;
+ u32 p2_p3_dir_clr;
+ u32 p2_p3_dir_state;
+ /* Now back to 'one register for one port' */
+ u32 p2_inp_state;
+ u32 p2_outp_set;
+ u32 p2_outp_clr;
+ u32 reserved1[6];
+ u32 p0_inp_state;
+ u32 p0_outp_set;
+ u32 p0_outp_clr;
+ u32 p0_outp_state;
+ u32 p0_dir_set;
+ u32 p0_dir_clr;
+ u32 p0_dir_state;
+ u32 reserved2;
+ u32 p1_inp_state;
+ u32 p1_outp_set;
+ u32 p1_outp_clr;
+ u32 p1_outp_state;
+ u32 p1_dir_set;
+ u32 p1_dir_clr;
+ u32 p1_dir_state;
+};