diff options
| author | Gabor Juhos <juhosg@openwrt.org> | 2013-01-24 06:27:51 +0000 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2013-01-27 16:39:43 +0100 |
| commit | 5b7dd8163d517c8f52971bc16fe92f831553d2bb (patch) | |
| tree | 2f0e010789470130e582a5548d1641bc694b9d6d /arch/mips | |
| parent | 14fdd1a8bfd97de46042cda6086347b0d66461d4 (diff) | |
MIPS: start.S: fix boundary check in relocate_code
The loop code copies more data with one than
necessary due to the 'ble' instuction. Use the
'blt' instruction instead to fix that.
Due to the lack of suitable hardware the Xburst
specific code is compile tested only. However the
change is quite obvious.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/cpu/mips32/start.S | 2 | ||||
| -rw-r--r-- | arch/mips/cpu/mips64/start.S | 2 | ||||
| -rw-r--r-- | arch/mips/cpu/xburst/start.S | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 22a9c1bff5e..a4fc1ec0a48 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -313,7 +313,7 @@ relocate_code: lw t3, 0(t0) sw t3, 0(t1) addu t0, 4 - ble t0, t2, 1b + blt t0, t2, 1b addu t1, 4 /* If caches were enabled, we would have to flush them here. */ diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S index bc7e41eed52..aed82e1f07e 100644 --- a/arch/mips/cpu/mips64/start.S +++ b/arch/mips/cpu/mips64/start.S @@ -192,7 +192,7 @@ relocate_code: lw t3, 0(t0) sw t3, 0(t1) daddu t0, 4 - ble t0, t2, 1b + blt t0, t2, 1b daddu t1, 4 /* If caches were enabled, we would have to flush them here. */ diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S index 3a8280cb0ab..194d7452e1a 100644 --- a/arch/mips/cpu/xburst/start.S +++ b/arch/mips/cpu/xburst/start.S @@ -87,7 +87,7 @@ relocate_code: lw t3, 0(t0) sw t3, 0(t1) addu t0, 4 - ble t0, t2, 1b + blt t0, t2, 1b addu t1, 4 /* If caches were enabled, we would have to flush them here. */ |