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authorWolfgang Denk <wd@denx.de>2010-10-11 09:56:34 +0200
committerWolfgang Denk <wd@denx.de>2010-10-11 09:56:34 +0200
commit29840de6b6d322e9cca3d22d254a1d066afbef02 (patch)
treed73e08629803d5e11111c0e6c169acc622e1a1ba /arch/powerpc
parent02b117d42b1bff19b210ac258a1ef5cf58229274 (diff)
parentbfb707191a4332361f13f0fb3d99dd9986af8825 (diff)
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/cpu/mpc85xx/p4080_ids.c14
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h5
2 files changed, 14 insertions, 5 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
index a6cfaa5971..df2504802a 100644
--- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c
@@ -81,10 +81,16 @@ struct liodn_id_table fman2_liodn_tbl[] = {
#endif
struct liodn_id_table sec_liodn_tbl[] = {
- SET_SEC_JR_LIODN_ENTRY(0, 146, 154),
- SET_SEC_JR_LIODN_ENTRY(1, 147, 155),
- SET_SEC_JR_LIODN_ENTRY(2, 178, 186),
- SET_SEC_JR_LIODN_ENTRY(3, 179, 187),
+ /*
+ * We assume currently that all JR are in the same partition
+ * and as such they need to represent the same LIODN due to
+ * a 4080 rev.2 h/w requirement that DECOs sharing from themselves
+ * or from another DECO have the two Non-SEQ LIODN values equal
+ */
+ SET_SEC_JR_LIODN_ENTRY(0, 146, 154), /* (0, 146, 154), */
+ SET_SEC_JR_LIODN_ENTRY(1, 146, 154), /* (1, 147, 155), */
+ SET_SEC_JR_LIODN_ENTRY(2, 146, 154), /* (2, 178, 186), */
+ SET_SEC_JR_LIODN_ENTRY(3, 146, 154), /* (3, 179, 187), */
SET_SEC_RTIC_LIODN_ENTRY(a, 144),
SET_SEC_RTIC_LIODN_ENTRY(b, 145),
SET_SEC_RTIC_LIODN_ENTRY(c, 176),
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 3dd2b7f53a..30c64ebb17 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1589,7 +1589,9 @@ typedef struct cpc_corenet {
u32 cpcerreaddr; /* error extended address */
u32 cpcerraddr; /* error address */
u32 cpcerrctl; /* error control */
- u32 res9[105]; /* pad out to 4k */
+ u32 res9[41]; /* pad out to 4k */
+ u32 cpchdbcr0; /* hardware debug control register 0 */
+ u32 res10[63]; /* pad out to 4k */
} cpc_corenet_t;
#define CPC_CSR0_CE 0x80000000 /* Cache Enable */
@@ -1616,6 +1618,7 @@ typedef struct cpc_corenet {
#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
#define CPC_SRCR0_SRAMEN 0x00000001
#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
+#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
#endif /* CONFIG_SYS_FSL_CPC */
/* Global Utilities Block */