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authorTom Rini <trini@konsulko.com>2019-12-18 07:20:19 -0500
committerTom Rini <trini@konsulko.com>2019-12-18 07:20:19 -0500
commitc0912f9bbfb26dd03d189953678691b799d35b6e (patch)
treef879600cd26b8d4678a174854b623941e5dc2ada /arch/x86/include/asm/processor.h
parent533c9f5714bdba79dc6f2629284d4c1a08a611d1 (diff)
parenta1d6dc3f84071f05574044f337dbdca70fae495d (diff)
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next
- Various x86 common codes updated for TPL/SPL - I2C designware driver updated for PCI - ICH SPI driver updated to support Apollo Lake - Add Intel FSP2 base support - Intel Apollo Lake platform specific drivers support - Add a new board Google Chromebook Coral
Diffstat (limited to 'arch/x86/include/asm/processor.h')
-rw-r--r--arch/x86/include/asm/processor.h12
1 files changed, 5 insertions, 7 deletions
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index f1d9977bcb3..d7b68367861 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -25,8 +25,6 @@
/* Length of the public header on Intel microcode blobs */
#define UCODE_HEADER_LEN 0x30
-#ifndef __ASSEMBLY__
-
/*
* This register is documented in (for example) the Intel Atom Processor E3800
* Product Family Datasheet in "PCU - Power Management Controller (PMC)".
@@ -37,11 +35,11 @@
*/
#define IO_PORT_RESET 0xcf9
-enum {
- SYS_RST = 1 << 1, /* 0 for soft reset, 1 for hard reset */
- RST_CPU = 1 << 2, /* initiate reset */
- FULL_RST = 1 << 3, /* full power cycle */
-};
+#define SYS_RST (1 << 1) /* 0 for soft reset, 1 for hard reset */
+#define RST_CPU (1 << 2) /* initiate reset */
+#define FULL_RST (1 << 3) /* full power cycle */
+
+#ifndef __ASSEMBLY__
static inline __attribute__((always_inline)) void cpu_hlt(void)
{