Initial Toradex Colibri T20 L4T R15 support.T20_LinuxImageV2.0Alpha1_20120808

15 files changed, 98 insertions, 18 deletions

diff --git a/arch/arm/cpu/armv7/tegra-common/ap20.c b/arch/arm/cpu/armv7/tegra-common/ap20.c
index 517fba30b15..4f54dd61218 100644
--- a/arch/arm/cpu/armv7/tegra-common/ap20.c
+++ b/arch/arm/cpu/armv7/tegra-common/ap20.c
@@ -146,6 +146,7 @@ int ap20_get_num_cpus(void)
 	return ap20_get_family() == TEGRA_FAMILY_T3x ? 4 : 2;
 }
 
+/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
 int ap20_cpu_is_cortexa9(void)
 {
 	u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
@@ -180,7 +181,7 @@ static int pllx_set_rate(struct clk_pll *pll , u32 divn, u32 divm, u32 divp,
 	bf_update(PLL_DIVM, reg, divm);
 	bf_update(PLL_DIVN, reg, divn);
 	bf_update(PLL_DIVP, reg, divp);
-	bf_update(PLL_BYPASS, reg, 0);
+	bf_update(PLL_BYPASS, reg, 0);	/* Disable BYPASS */
 	writel(reg, &pll->pll_base);
 
 	/* Set cpcon to PLLX_MISC */
@@ -197,6 +198,9 @@ static int pllx_set_rate(struct clk_pll *pll , u32 divn, u32 divm, u32 divp,
 	return 0;
 }
 
+/* U-Boot treats all errors as warnings,  &clkrst->crc_pll[CLOCK_ID_XCPU] uses
+   a subscript out of range. The pragma disables the warning */
+#pragma GCC diagnostic warning "-Warray-bounds"
 void ap20_init_pllx(int slow)
 {
 	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
@@ -332,10 +336,10 @@ static void enable_cpu_power_rail(enum tegra_family_t family)
 
 	if (family == TEGRA_FAMILY_T3x) {
 		/*
-		* TODO(sjg):
-		* Fow now we do this here. We need to find out what this is
+		 * TODO(sjg):
+		 * For now we do this here. We need to find out what this is
 		 * doing, tidy up the code and find a better place for it.
-		*/
+		 */
 		tegra_i2c_ll_write_addr(0x005a, 0x0002);
 		tegra_i2c_ll_write_data(0x2328, 0x0a02);
 		udelay(1000);
@@ -384,11 +388,11 @@ void t30_init_clocks(void)
 {
 #if defined(CONFIG_TEGRA3)
 	/*
-	* Sadly our clock functions don't support the V and W clocks of T30
-	* yet, as well as a few other functions, so use low-level register
-	* access for now. This eventual removable of low-level code from
-	* ap20.c is the same process we went through for T20.
-	*/
+	 * Sadly our clock functions don't support the V and W clocks of T30
+	 * yet, as well as a few other functions, so use low-level register
+	 * access for now. This eventual removable of low-level code from
+	 * ap20.c is the same process we went through for T20.
+	 */
 	struct clk_rst_ctlr *clkrst =
 			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
diff --git a/arch/arm/cpu/armv7/tegra-common/board.c b/arch/arm/cpu/armv7/tegra-common/board.c
index 5a57298db7e..5f772b55b66 100644
--- a/arch/arm/cpu/armv7/tegra-common/board.c
+++ b/arch/arm/cpu/armv7/tegra-common/board.c
@@ -1,6 +1,8 @@
 /*
  *  (C) Copyright 2010,2011
  *  NVIDIA Corporation <www.nvidia.com>
+ *  (C) Copyright 2012
+ *  Toradex, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -37,6 +39,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 unsigned int board_query_sdram_size(void)
 {
+#ifndef CONFIG_COLIBRI_T20
 	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 	u32 reg;
 
@@ -60,6 +63,15 @@ unsigned int board_query_sdram_size(void)
 	default:
 		return 0x40000000;	/* 1GB */
 	}
+#else /* CONFIG_COLIBRI_T20 */
+	/* Colibri T20 does not use OdmData */
+	u32 *pa_emc_adr_cfg = (void *)NV_PA_EMC_ADR_CFG_BASE;
+
+	u32 reg = readl(pa_emc_adr_cfg);
+
+	/* 4 MB shifted by EMEM_DEVSIZE */
+	return (4 << 20) << ((reg & EMEM_DEVSIZE_MASK) >> EMEM_DEVSIZE_SHIFT);
+#endif /* CONFIG_COLIBRI_T20 */
 }
 
 #if defined(CONFIG_DISPLAY_BOARDINFO) || defined(CONFIG_DISPLAY_BOARDINFO_LATE)
diff --git a/arch/arm/cpu/armv7/tegra-common/clock.c b/arch/arm/cpu/armv7/tegra-common/clock.c
index 01caab6b9fa..0d1f2091657 100644
--- a/arch/arm/cpu/armv7/tegra-common/clock.c
+++ b/arch/arm/cpu/armv7/tegra-common/clock.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2012 Toradex, Inc.
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -493,6 +494,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
  *	SPDIF - which is both 0x08 and 0x0c
  *
  */
+//I believe above comment concerning SPDIF is bogus
 #define NONE(name) (-1)
 #define OFFSET(name, value) PERIPHC_ ## name
 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
@@ -1361,11 +1363,14 @@ int clock_early_init(ulong pllp_base)
 		osc_freq_mhz = 12;
 		break;
 
+	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+		osc_freq_mhz = 13;
+		break;
+
 	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
 		osc_freq_mhz = 26;
 		break;
 
-	case CLOCK_OSC_FREQ_13_0:
 	case CLOCK_OSC_FREQ_19_2:
 	default:
 		/*
diff --git a/arch/arm/cpu/armv7/tegra-common/display.c b/arch/arm/cpu/armv7/tegra-common/display.c
index 2f12084447c..55ea13e1289 100644
--- a/arch/arm/cpu/armv7/tegra-common/display.c
+++ b/arch/arm/cpu/armv7/tegra-common/display.c
@@ -117,7 +117,7 @@ static int update_display_mode(struct dc_disp_reg *disp,
 	/*
 	 * The pixel clock divider is in 7.1 format (where the bottom bit
 	 * represents 0.5). Here we calculate the divider needed to get from
-	 * the display clock (typically 600MHz for tegra2 and 216MHZ
+	 * the display clock (typically 600MHz for tegra2 and 216MHz
 	 * for tegra3) to the pixel clock. We round up or down as requried.
 	 */
 #if defined(CONFIG_TEGRA2)
diff --git a/arch/arm/cpu/armv7/tegra-common/pwfm.c b/arch/arm/cpu/armv7/tegra-common/pwfm.c
index 5ef4363082f..bdc16207240 100644
--- a/arch/arm/cpu/armv7/tegra-common/pwfm.c
+++ b/arch/arm/cpu/armv7/tegra-common/pwfm.c
@@ -30,8 +30,11 @@ void pwfm_setup(struct pwfm_ctlr *pwfm, int enable, int pulse_width,
 {
 	u32 reg;
 
-	reg = bf_pack(PWFM_ENABLE, enable) |
-		bf_pack(PWFM_WIDTH, pulse_width) |
-		bf_pack(PWFM_DIVIDER, freq_divider);
-	writel(reg, &pwfm->control);
+	if(pwfm != NULL)
+	{
+		reg = bf_pack(PWFM_ENABLE, enable) |
+			bf_pack(PWFM_WIDTH, pulse_width) |
+			bf_pack(PWFM_DIVIDER, freq_divider);
+		writel(reg, &pwfm->control);
+	}
 }
diff --git a/arch/arm/cpu/armv7/tegra3/warmboot_avp.c b/arch/arm/cpu/armv7/tegra3/warmboot_avp.c
index 02772d42c16..02d320aed75 100644
--- a/arch/arm/cpu/armv7/tegra3/warmboot_avp.c
+++ b/arch/arm/cpu/armv7/tegra3/warmboot_avp.c
@@ -81,7 +81,7 @@ void wb_start(void)
 
 	reg = SCLK_SWAKE_FIQ_SRC_CLKM | SCLK_SWAKE_IRQ_SRC_CLKM |
 		SCLK_SWAKE_RUN_SRC_CLKM | SCLK_SWAKE_IDLE_SRC_CLKM |
-		SCLK_SYS_STATE_RUN;
+		SCLK_SYS_CPU_STATE_RUN;
 	writel(reg, &clkrst->crc_sclk_brst_pol);
 
 	/* Update PLLP output dividers for 408 MHz operation */
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index 6bf9cb61314..3233d3b9d0d 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -275,7 +275,7 @@ enum {
 #define SUPER_CDIV_ENB				(1 << 31)
 
 /* CRC_SCLK_BURST_POLICY_0 28h */
-#define SCLK_SYS_STATE_RUN			(2 << 28)
+#define SCLK_SYS_CPU_STATE_RUN			(2 << 28)
 #define SCLK_SWAKE_FIQ_SRC_CLKM			(0 << 12)
 #define SCLK_SWAKE_IRQ_SRC_CLKM			(0 << 8)
 #define SCLK_SWAKE_RUN_SRC_CLKM			(0 << 4)
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 471420136fa..c51a8014e01 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -56,6 +56,9 @@
 #define TEGRA_KBC_BASE		0x7000E200
 #define NV_PA_PMC_BASE		0x7000E400
 #define NV_PA_EMC_BASE		0x7000F400
+#define NV_PA_EMC_ADR_CFG_BASE	(NV_PA_EMC_BASE + 0x10)
+#define EMEM_DEVSIZE_MASK	(0xf << EMEM_DEVSIZE_SHIFT)
+#define EMEM_DEVSIZE_SHIFT	(16)
 #define NV_PA_FUSE_BASE		0x7000F800
 #define NV_PA_CSITE_BASE	0x70040000
 
diff --git a/arch/arm/include/asm/arch-tegra2/pmu.h b/arch/arm/include/asm/arch-tegra2/pmu.h
index 5baab7604a6..0faf07c3db4 100644
--- a/arch/arm/include/asm/arch-tegra2/pmu.h
+++ b/arch/arm/include/asm/arch-tegra2/pmu.h
@@ -54,4 +54,6 @@
 #define SM1_PWM_BIT		1
 #define SM2_PWM_BIT		2
 
+#define MAX_I2C_RETRY	3
+
 #endif	/* _ARCH_PMU_H_ */
diff --git a/arch/arm/include/asm/arch-tegra2/tegra.h b/arch/arm/include/asm/arch-tegra2/tegra.h
index 6284e22c3be..125e31ed88d 100644
--- a/arch/arm/include/asm/arch-tegra2/tegra.h
+++ b/arch/arm/include/asm/arch-tegra2/tegra.h
@@ -36,6 +36,8 @@
 #define NV_PA_USB1_BASE		0xC5000000
 #define NV_PA_USB3_BASE		0xC5008000
 
+#define NV_APB_MISC_BASE    0x70000000
+
 #include <asm/arch-tegra/tegra.h>
 
 #endif
diff --git a/arch/arm/include/asm/arch-tegra3/pmu.h b/arch/arm/include/asm/arch-tegra3/pmu.h
index e2ed1d0325e..f014a0f15e3 100644
--- a/arch/arm/include/asm/arch-tegra3/pmu.h
+++ b/arch/arm/include/asm/arch-tegra3/pmu.h
@@ -35,4 +35,6 @@
 #define PMU_LDO5_SEL(decivolts)	((decivolts - 10) * PMU_LDO5_SEL_0_1V_DELTA + \
 				 PMU_LDO5_SEL_1_0V)
 
+#define MAX_I2C_RETRY	3
+
 #endif	/* _ARCH_PMU_H_ */
diff --git a/arch/arm/include/asm/arch-tegra3/pmu_core.h b/arch/arm/include/asm/arch-tegra3/pmu_core.h
new file mode 100644
index 00000000000..48c61e04376
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra3/pmu_core.h
@@ -0,0 +1,36 @@
+/*
+ *  (C) Copyright 2012
+ *  Toradex AG <www.toradex.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* definitions for TPS62360 / TPS62362 */
+#ifndef _PMU_CORE_H_
+#define _PMU_CORE_H_
+
+#define DVC_I2C_BUS_NUMBER	0
+#define PMU_CORE_I2C_ADDRESS		0x60
+
+#define PMU_CORE_VOLTAGE_START_REG	0x02
+#define PMU_CORE_VOLTAGE_DVFS_REG	0x00
+
+#define VDD_CORE_NOMINAL_T30	43	/* 1.2V = 0.77V + x * 10mV */
+
+#endif	/* PMU_CORE_H */
diff --git a/arch/arm/include/asm/arch-tegra3/tegra.h b/arch/arm/include/asm/arch-tegra3/tegra.h
index 62998fdbf18..046e58cddf6 100644
--- a/arch/arm/include/asm/arch-tegra3/tegra.h
+++ b/arch/arm/include/asm/arch-tegra3/tegra.h
@@ -38,6 +38,8 @@
 #define NV_PA_USB2_BASE		0x7D004000
 #define NV_PA_USB3_BASE		0x7D008000
 
+#define NV_APB_MISC_BASE    0x70000000
+
 #include <asm/arch-tegra/tegra.h>
 
 #endif
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index c72f6400d1f..800f5fe6a58 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -79,6 +79,14 @@ typedef	struct	global_data {
 	const void	*blob;		/* Our device tree, NULL if none */
 	void		**jt;		/* jump table */
 	char		env_buf[32];	/* buffer for getenv() before reloc. */
+#if defined(CONFIG_COLIBRI_T20) || defined(CONFIG_COLIBRI_T30)
+	unsigned env_offset; /* offset to the u-boot environment in mass storage */
+	unsigned conf_blk_offset; /* offset to the Toradex config block in mass storage */
+	unsigned conf_blk_offset2; /* offset to the Toradex config block (WinCE) in mass storage */
+	unsigned kernel_offset; /* offset to the kernel in mass storage */
+	unsigned rootfs_size; /* size of the rootfs in mass storage */
+	unsigned rootfs_offset; /* offset to the rootfs in mass storage */
+#endif
 } gd_t;
 
 /*
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 339cb08ae50..b46bec1ae9e 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -210,7 +210,8 @@ static int bootm_linux_fdt(int machid, bootm_headers_t *images)
 	if (ret)
 		return ret;
 
-#ifdef CONFIG_OF_UPDATE_FDT_BEFORE_BOOT
+#if defined(CONFIG_CHROMEOS) && defined(CONFIG_OF_UPDATE_FDT_BEFORE_BOOT)
+//ToDo: this might be helpfull for NAND stuff
 	/* this must be earlier than boot_relocate_fdt */
 	ret = fit_update_fdt_before_boot(*of_flat_tree, &of_size);
 	if (ret)