diff options
| author | Michal Simek <monstr@monstr.eu> | 2014-04-25 12:21:04 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2014-05-14 07:43:35 +0200 |
| commit | eb8c54bfaabec7b8ba65a054f6c3e37572288ae9 (patch) | |
| tree | e85430dc520a89c97c0d1ec4deaf901e9e04b033 /arch | |
| parent | 3cc3fa8672705e609ccd25348438453bd8de07fd (diff) | |
ARM: zynq: ehci: Added USB host driver support
Added USB host driver for zynq.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/zynq/slcr.c | 24 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-zynq/hardware.h | 2 |
2 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 51894f92397..934ccc31c86 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -14,6 +14,8 @@ #define SLCR_LOCK_MAGIC 0x767B #define SLCR_UNLOCK_MAGIC 0xDF0D +#define SLCR_USB_L1_SEL 0x04 + #define SLCR_IDCODE_MASK 0x1F000 #define SLCR_IDCODE_SHIFT 12 @@ -34,7 +36,29 @@ struct zynq_slcr_mio_get_status { u32 check_val; }; +static const int usb0_pins[] = { + 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39 +}; + +static const int usb1_pins[] = { + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51 +}; + static const struct zynq_slcr_mio_get_status mio_periphs[] = { + { + "usb0", + usb0_pins, + ARRAY_SIZE(usb0_pins), + SLCR_USB_L1_SEL, + SLCR_USB_L1_SEL, + }, + { + "usb1", + usb1_pins, + ARRAY_SIZE(usb1_pins), + SLCR_USB_L1_SEL, + SLCR_USB_L1_SEL, + }, }; static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */ diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index a9d091f141e..2aede0c552c 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -23,6 +23,8 @@ #define ZYNQ_SPI_BASEADDR1 0xE0007000 #define ZYNQ_DDRC_BASEADDR 0xF8006000 #define ZYNQ_EFUSE_BASEADDR 0xF800D000 +#define ZYNQ_USB_BASEADDR0 0xE0002000 +#define ZYNQ_USB_BASEADDR1 0xE0003000 /* Bootmode setting values */ #define ZYNQ_BM_MASK 0x7 |