powerpc: ppc4xx: remove board support for bluestone

This board has been orphaned for more than 6 months.

It is the last board defining CONFIG_APM821XX.
The code inside #ifdef CONFIG_APM821XX should be removed too.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

11 files changed, 18 insertions, 180 deletions

diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index d525ad3bd64..56abe8dc56f 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -52,9 +52,6 @@ config TARGET_ACADIA
 config TARGET_BAMBOO
 	bool "Support bamboo"
 
-config TARGET_BLUESTONE
-	bool "Support bluestone"
-
 config TARGET_BUBINGA
 	bool "Support bubinga"
 
@@ -239,7 +236,6 @@ endchoice
 
 source "board/amcc/acadia/Kconfig"
 source "board/amcc/bamboo/Kconfig"
-source "board/amcc/bluestone/Kconfig"
 source "board/amcc/bubinga/Kconfig"
 source "board/amcc/canyonlands/Kconfig"
 source "board/amcc/ebony/Kconfig"
diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c
index 6a485264e7c..aab65d405c5 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu.c
@@ -234,20 +234,6 @@ static char *bootstrap_str[] = {
 };
 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 #endif
-#if defined(CONFIG_APM821XX)
-#define SDR0_PINSTP_SHIFT       29
-static char *bootstrap_str[] = {
-	"RESERVED",
-	"RESERVED",
-	"RESERVED",
-	"NAND (8 bits)",
-	"NOR  (8 bits)",
-	"NOR  (8 bits) w/PLL Bypassed",
-	"I2C (Addr 0x54)",
-	"I2C (Addr 0x52)",
-};
-static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
-#endif
 
 #if defined(SDR0_PINSTP_SHIFT)
 static int bootstrap_option(void)
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index 0b27d2912d1..22561231cb8 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -284,7 +284,7 @@ cpu_init_f (void)
 	reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
 
 #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \
-    !defined(CONFIG_APM821XX) &&!defined(CONFIG_SYS_4xx_GPIO_TABLE)
+    !defined(CONFIG_SYS_4xx_GPIO_TABLE)
 	/*
 	 * GPIO0 setup (select GPIO or alternate function)
 	 */
@@ -440,7 +440,7 @@ cpu_init_f (void)
 #if defined(CONFIG_405EX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
-    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
+    defined(CONFIG_460SX)
 	/*
 	 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
 	 */
diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c
index 4baee7774c5..3e1a7016d94 100644
--- a/arch/powerpc/cpu/ppc4xx/speed.c
+++ b/arch/powerpc/cpu/ppc4xx/speed.c
@@ -171,7 +171,7 @@ ulong get_PCI_freq (void)
 #elif defined(CONFIG_440)
 
 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
+    defined(CONFIG_460SX)
 static u8 pll_fwdv_multi_bits[] = {
 	/* values for:  1 - 16 */
 	0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c,
@@ -232,78 +232,6 @@ u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv)
 	return 0;
 }
 
-#if defined(CONFIG_APM821XX)
-
-void get_sys_info(sys_info_t *sysInfo)
-{
-	unsigned long plld;
-	unsigned long temp;
-	unsigned long mul;
-	unsigned long cpudv;
-	unsigned long plb2dv;
-	unsigned long ddr2dv;
-
-	/* Calculate Forward divisor A and Feeback divisor */
-	mfcpr(CPR0_PLLD, plld);
-
-	temp = CPR0_PLLD_FWDVA(plld);
-	sysInfo->pllFwdDivA = get_cpr0_fwdv(temp);
-
-	temp = CPR0_PLLD_FDV(plld);
-	sysInfo->pllFbkDiv = get_cpr0_fbdv(temp);
-
-	/* Calculate OPB clock divisor */
-	mfcpr(CPR0_OPBD, temp);
-	temp = CPR0_OPBD_OPBDV(temp);
-	sysInfo->pllOpbDiv = temp ? temp : 4;
-
-	/* Calculate Peripheral clock divisor */
-	mfcpr(CPR0_PERD, temp);
-	temp = CPR0_PERD_PERDV(temp);
-	sysInfo->pllExtBusDiv = temp ? temp : 4;
-
-	/* Calculate CPU clock divisor */
-	mfcpr(CPR0_CPUD, temp);
-	temp = CPR0_CPUD_CPUDV(temp);
-	cpudv = temp ? temp : 8;
-
-	/* Calculate PLB2 clock divisor */
-	mfcpr(CPR0_PLB2D, temp);
-	temp = CPR0_PLB2D_PLB2DV(temp);
-	plb2dv = temp ? temp : 4;
-
-	/* Calculate DDR2 clock divisor */
-	mfcpr(CPR0_DDR2D, temp);
-	temp = CPR0_DDR2D_DDR2DV(temp);
-	ddr2dv = temp ? temp : 4;
-
-	/* Calculate 'M' based on feedback source */
-	mfcpr(CPR0_PLLC, temp);
-	temp = CPR0_PLLC_SEL(temp);
-	if (temp == 0) {
-		/* PLL internal feedback */
-		mul = sysInfo->pllFbkDiv;
-	} else {
-		/* PLL PerClk feedback */
-		mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv
-			* plb2dv * 2 * sysInfo->pllOpbDiv *
-			  sysInfo->pllExtBusDiv;
-	}
-
-	/* Now calculate the individual clocks */
-	sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1);
-	sysInfo->freqProcessor = sysInfo->freqVCOMhz /
-		sysInfo->pllFwdDivA / cpudv;
-	sysInfo->freqPLB = sysInfo->freqVCOMhz /
-		sysInfo->pllFwdDivA / cpudv / plb2dv / 2;
-	sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv;
-	sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv;
-	sysInfo->freqDDR = sysInfo->freqVCOMhz /
-		sysInfo->pllFwdDivA / cpudv / ddr2dv / 2;
-	sysInfo->freqUART = sysInfo->freqPLB;
-}
-
-#else
 /*
  * AMCC_TODO: verify this routine against latest EAS, cause stuff changed
  *            with latest EAS
@@ -361,7 +289,6 @@ void get_sys_info (sys_info_t * sysInfo)
 
 	return;
 }
-#endif
 
 #elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 11b55d5a56e..09a02d771c2 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -664,8 +664,7 @@ _start:
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460SX)
 	mtdcr	L2_CACHE_CFG,r0		/* Ensure L2 Cache is off */
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-      defined(CONFIG_APM821XX)
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	lis	r1, 0x0000
 	ori	r1,r1,0x0008		/* Set L2_CACHE_CFG[RDBW]=1 */
 	mtdcr	L2_CACHE_CFG,r1
@@ -694,7 +693,7 @@ _start:
 	ori	r1,r1, 0x0980		/* fourth 64k */
 	mtdcr	ISRAM0_SB3CR,r1
 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
-      defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
+      defined(CONFIG_460GT)
 	lis	r1,0x0000		/* BAS = X_0000_0000 */
 	ori	r1,r1,0x0984		/* first 64k */
 	mtdcr	ISRAM0_SB0CR,r1
@@ -707,8 +706,7 @@ _start:
 	lis	r1, 0x0003
 	ori	r1,r1, 0x0984		/* fourth 64k */
 	mtdcr	ISRAM0_SB3CR,r1
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_APM821XX)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	lis	r2,0x7fff
 	ori	r2,r2,0xffff
 	mfdcr	r1,ISRAM1_DPC
diff --git a/arch/powerpc/include/asm/apm821xx.h b/arch/powerpc/include/asm/apm821xx.h
deleted file mode 100644
index d027866d3d9..00000000000
--- a/arch/powerpc/include/asm/apm821xx.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (c) 2010, Applied Micro Circuits Corporation
- * Author: Tirumala R Marri <tmarri@apm.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _APM821XX_H_
-#define _APM821XX_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */
-
-/* Memory mapped registers */
-#define CONFIG_SYS_PERIPHERAL_BASE	0xEF600000
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-
-#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-
-#define SDR0_SRST0_DMC		0x00200000
-#define SDR0_SRST1_AHB		0x00000040      /* PLB4XAHB bridge */
-
-/* AHB config. */
-#define AHB_TOP			0xA4
-#define AHB_BOT			0xA5
-
-/* clk divisors */
-#define PLLSYS0_FWD_DIV_A_MASK	0x000000f0	/* Fwd Div A */
-#define PLLSYS0_FWD_DIV_B_MASK	0x0000000f	/* Fwd Div B */
-#define PLLSYS0_FB_DIV_MASK	0x0000ff00	/* Feedback divisor */
-#define PLLSYS0_OPB_DIV_MASK	0x0c000000	/* OPB Divisor */
-#define PLLSYS0_EPB_DIV_MASK	0x00000300      /* EPB divisor */
-#define PLLSYS0_EXTSL_MASK	0x00000080      /* PerClk feedback path */
-#define PLLSYS0_PLBEDV0_DIV_MASK	0xe0000000/* PLB Early Clk Div*/
-#define PLLSYS0_PERCLK_DIV_MASK	0x03000000	/* Peripheral Clk Divisor */
-#define PLLSYS0_SEL_MASK	0x18000000	/* 0 = PLL, 1 = PerClk */
-
-/*
-   + * Clocking Controller
-   + */
-#define CPR0_CLKUPD	0x0020
-#define CPR0_PLLC	0x0040
-#define CPR0_PLLC_SEL(pllc)		(((pllc) & 0x01000000) >> 24)
-#define CPR0_PLLD	0x0060
-#define CPR0_PLLD_FDV(plld)		(((plld) & 0xff000000) >> 24)
-#define CPR0_PLLD_FWDVA(plld)		(((plld) & 0x000f0000) >> 16)
-#define CPR0_CPUD	0x0080
-#define CPR0_CPUD_CPUDV(cpud)		(((cpud) & 0x07000000) >> 24)
-#define CPR0_PLB2D	0x00a0
-#define CPR0_PLB2D_PLB2DV(plb2d)	(((plb2d) & 0x06000000) >> 25)
-#define CPR0_OPBD	0x00c0
-#define CPR0_OPBD_OPBDV(opbd)		(((opbd) & 0x03000000) >> 24)
-#define CPR0_PERD	0x00e0
-#define CPR0_PERD_PERDV(perd)		(((perd) & 0x03000000) >> 24)
-#define CPR0_DDR2D	0x0100
-#define CPR0_DDR2D_DDR2DV(ddr2d) 	(((ddr2d) & 0x06000000) >> 25)
-#define CLK_ICFG	0x0140
-
-#endif /* _APM821XX_H_ */
diff --git a/arch/powerpc/include/asm/ppc4xx-ebc.h b/arch/powerpc/include/asm/ppc4xx-ebc.h
index 07a3fe033fc..952783f9619 100644
--- a/arch/powerpc/include/asm/ppc4xx-ebc.h
+++ b/arch/powerpc/include/asm/ppc4xx-ebc.h
@@ -53,8 +53,7 @@
 #define EBC_NUM_BANKS	6
 #endif
 
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_APM821XX)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 #define EBC_NUM_BANKS	3
 #endif
 
diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h
index 4d1106b1242..2ae399f2488 100644
--- a/arch/powerpc/include/asm/ppc4xx-isram.h
+++ b/arch/powerpc/include/asm/ppc4xx-isram.h
@@ -8,8 +8,7 @@
 /*
  * Internal SRAM
  */
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_APM821XX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define ISRAM0_DCR_BASE 0x380
 #else
 #define ISRAM0_DCR_BASE 0x020
@@ -26,8 +25,7 @@
 #define ISRAM0_REVID	(ISRAM0_DCR_BASE+0x09)	/* SRAM bus revision id reg */
 #define ISRAM0_DPC	(ISRAM0_DCR_BASE+0x0a)	/* SRAM data parity check reg */
 
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_APM821XX)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define ISRAM1_DCR_BASE 0x0B0
 #define ISRAM1_SB0CR	(ISRAM1_DCR_BASE+0x00)	/* SRAM1 bank config 0*/
 #define ISRAM1_BEAR	(ISRAM1_DCR_BASE+0x04)	/* SRAM1 bus error addr reg */
@@ -41,8 +39,6 @@
 
 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define ISRAM1_SIZE 0x0984 /* OCM size 64k */
-#elif defined(CONFIG_APM821XX)
-#define ISRAM1_SIZE 0x0784 /* OCM size 32k */
 #endif
 
 /*
@@ -51,7 +47,7 @@
 #if defined (CONFIG_440GX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
+    defined(CONFIG_460SX)
 #define L2_CACHE_BASE	0x030
 #define L2_CACHE_CFG	(L2_CACHE_BASE+0x00)	/* L2 Cache Config      */
 #define L2_CACHE_CMD	(L2_CACHE_BASE+0x01)	/* L2 Cache Command     */
diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h
index 12d6d038c7b..e6fed83bf1c 100644
--- a/arch/powerpc/include/asm/ppc4xx-sdram.h
+++ b/arch/powerpc/include/asm/ppc4xx-sdram.h
@@ -276,7 +276,7 @@
  */
 #if defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
+    defined(CONFIG_460SX)
 #define SDRAM_RXBAS_SDBA_MASK		0xFFE00000	/* Base address	*/
 #define SDRAM_RXBAS_SDBA_ENCODE(n)	((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
 #define SDRAM_RXBAS_SDBA_DECODE(n)	((((phys_size_t)(n)) & 0xFFE00000) << 2)
@@ -349,7 +349,7 @@
 /*
  * Memory controller registers
  */
-#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX)
+#if defined(CONFIG_405EX)
 #define SDRAM_BESR	0x00	/* PLB bus error status (read/clear)         */
 #define SDRAM_BESRT	0x01	/* PLB bus error status (test/set)           */
 #define SDRAM_BEARL	0x02	/* PLB bus error address low                 */
@@ -359,9 +359,9 @@
 #define SDRAM_PLBOPT	0x08	/* PLB slave options                         */
 #define SDRAM_PUABA	0x09	/* PLB upper address base                    */
 #define SDRAM_MCSTAT	0x1F	/* memory controller status                  */
-#else /* CONFIG_405EX || CONFIG_APM821XX */
+#else /* CONFIG_405EX */
 #define SDRAM_MCSTAT	0x14	/* memory controller status                  */
-#endif /* CONFIG_405EX || CONFIG_APM821XX */
+#endif /* CONFIG_405EX */
 #define SDRAM_MCOPT1	0x20	/* memory controller options 1               */
 #define SDRAM_MCOPT2	0x21	/* memory controller options 2               */
 #define SDRAM_MODT0	0x22	/* on die termination for bank 0             */
@@ -407,12 +407,12 @@
 #define SDRAM_MEMODE	0x89	/* memory extended mode                      */
 #define SDRAM_ECCES	0x98	/* ECC error status                          */
 #define SDRAM_CID	0xA4	/* core ID                                   */
-#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX)
+#if !defined(CONFIG_405EX)
 #define SDRAM_RID	0xA8	/* revision ID                               */
 #endif
 #define SDRAM_FCSR	0xB0	/* feedback calibration status               */
 #define SDRAM_RTSR	0xB1	/* run time status tracking                  */
-#if  defined(CONFIG_405EX) || defined(CONFIG_APM821XX)
+#if  defined(CONFIG_405EX)
 #define SDRAM_RID	0xF8	/* revision ID                               */
 #endif
 
diff --git a/arch/powerpc/include/asm/ppc4xx-uic.h b/arch/powerpc/include/asm/ppc4xx-uic.h
index 05b4690a5c1..58e65c1336f 100644
--- a/arch/powerpc/include/asm/ppc4xx-uic.h
+++ b/arch/powerpc/include/asm/ppc4xx-uic.h
@@ -15,7 +15,7 @@
  */
 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
+    defined(CONFIG_460SX)
 #define UIC_MAX		4
 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_405EX)
@@ -236,8 +236,7 @@
 #define VECNUM_ETH0		(32 + 28)
 #endif /* CONFIG_440SPE */
 
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_APM821XX)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 /* UIC 0 */
 #define VECNUM_UIC2NCI		10
 #define VECNUM_UIC2CI		11
diff --git a/arch/powerpc/include/asm/ppc4xx.h b/arch/powerpc/include/asm/ppc4xx.h
index e6a3bff079e..b8b0ff9f25b 100644
--- a/arch/powerpc/include/asm/ppc4xx.h
+++ b/arch/powerpc/include/asm/ppc4xx.h
@@ -56,10 +56,6 @@
 #include <asm/ppc460sx.h>
 #endif
 
-#if defined(CONFIG_APM821XX)
-#include <asm/apm821xx.h>
-#endif
-
 /*
  * Common registers for all SoC's
  */