diff options
| author | Breno Matheus Lima <breno.lima@nxp.com> | 2019-05-07 20:19:17 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-06-27 14:10:40 +0200 |
| commit | 5760069ae8dd4dd36ea44b5a9890bd6e4bf09382 (patch) | |
| tree | 0dc7f854700c535b93ca6db8b0f5f15173331e4d /arch | |
| parent | 36adc9a06f64bffc327457418b5b6506ad1d18b4 (diff) | |
mx6sl: hab: Fix pu_irom_mmu_enabled address
According to hab.c code we have to notify the ROM code if the MMU is
enabled or not. This is achieved by setting the "pu_irom_mmu_enabled"
to 0x1.
The current address in hab.c code is wrong for i.MX6SL, according to ROM
map file the correct address is 0x00901c60.
As we are writing in the wrong address the ROM code is not flushing the
caches when needed, and the following HAB event is observed in certain
scenarios:
--------- HAB Event 1 -----------------
event data:
0xdb 0x00 0x14 0x41 0x33 0x18 0xc0 0x00
0xca 0x00 0x0c 0x00 0x01 0xc5 0x00 0x00
0x00 0x00 0x07 0xe4
STS = HAB_FAILURE (0x33)
RSN = HAB_INV_SIGNATURE (0x18)
CTX = HAB_CTX_COMMAND (0xC0)
ENG = HAB_ENG_ANY (0x00)
Update MX6SL_PU_IROM_MMU_EN_VAR to address this issue.
Reported-by: Frank Zhang <frank.zhang@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/hab.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index d42a15e8772..24d16299e8d 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -17,7 +17,7 @@ #define ALIGN_SIZE 0x1000 #define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8 #define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0 -#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18 +#define MX6SL_PU_IROM_MMU_EN_VAR 0x00901c60 #define IS_HAB_ENABLED_BIT \ (is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \ (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)) |