MLK-23964-23 imx7ulp_evk: Enable the rm68200 mipi panel for splash screen

Update DTS for LCDIF, MIPI DSI and panel relevant nodes.
Enable the video drivers and splash screen in board codse

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 52d4c7c3e98d573f1c3e4e67e02dd4b08be6bee7)

5 files changed, 136 insertions, 21 deletions

diff --git a/arch/arm/dts/imx7ulp-evk.dts b/arch/arm/dts/imx7ulp-evk.dts
index 8f6a935e24..f900a81532 100644
--- a/arch/arm/dts/imx7ulp-evk.dts
+++ b/arch/arm/dts/imx7ulp-evk.dts
@@ -31,7 +31,7 @@
 		reg = <0x60000000 0x40000000>;
 	};
 
-	backlight {
+	backlight: backlight {
 		compatible = "gpio-backlight";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_backlight>;
@@ -47,6 +47,24 @@
 		#reset-cells = <0>;
 	};
 
+	dsi_host: dsi-host {
+		compatible = "northwest,mipi-dsi";
+		status = "okay";
+	};
+
+	rm68200_panel {
+		compatible = "raydium,rm68200";
+		reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
+		backlight = <&backlight>;
+		status = "okay";
+
+		port {
+			rm68200_from_dsim: endpoint {
+				remote-endpoint = <&dsim_to_rm68200>;
+			};
+		};
+	};
+
 	regulators {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -285,32 +303,21 @@
 };
 
 &lcdif {
+	#address-cells = <1>;
+	#size-cells = <0>;
 	status = "okay";
-	disp-dev = "mipi_dsi_northwest";
 	display = <&display0>;
 
 	display0: display@0 {
-		bits-per-pixel = <16>;
+		bits-per-pixel = <24>;
 		bus-width = <24>;
+	};
 
-		display-timings {
-			native-mode = <&timing0>;
-			timing0: timing0 {
-			clock-frequency = <9200000>;
-			hactive = <480>;
-			vactive = <272>;
-			hfront-porch = <8>;
-			hback-porch = <4>;
-			hsync-len = <41>;
-			vback-porch = <2>;
-			vfront-porch = <4>;
-			vsync-len = <10>;
-
-			hsync-active = <0>;
-			vsync-active = <0>;
-			de-active = <1>;
-			pixelclk-active = <0>;
-			};
+	lcdif_disp0: port@0 {
+		reg = <0>;
+
+		lcdif_to_dsim: endpoint {
+			remote-endpoint = <&dsim_from_lcdif>;
 		};
 	};
 };
@@ -345,11 +352,25 @@
 };
 
 &mipi_dsi {
+	#address-cells = <1>;
+	#size-cells = <0>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_mipi_dsi_reset>;
 	lcd_panel = "TRULY-WVGA-TFT3P5581E";
 	resets = <&mipi_dsi_reset>;
 	status = "okay";
+
+	port@0 {
+		dsim_from_lcdif: endpoint {
+			remote-endpoint = <&lcdif_to_dsim>;
+		};
+	};
+
+	port@1 {
+		dsim_to_rm68200: endpoint {
+			remote-endpoint = <&rm68200_from_dsim>;
+		};
+	};
 };
 
 &lpuart4 { /* console */
diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi
index 9bb1396286..d154ef1155 100644
--- a/arch/arm/dts/imx7ulp.dtsi
+++ b/arch/arm/dts/imx7ulp.dtsi
@@ -488,6 +488,9 @@
 			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clks IMX7ULP_CLK_DSI>;
 			clock-names = "mipi_dsi_clk";
+			data-lanes-num = <2>;
+			phy-ref-clkfreq = <24000000>;
+			max-data-rate  = <800000000>;
 			sim = <&sim>;
 			status = "disabled";
 		};
diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h
index eb02a20fdc..ccd6a9a0a3 100644
--- a/arch/arm/include/asm/arch-mx7ulp/clock.h
+++ b/arch/arm/include/asm/arch-mx7ulp/clock.h
@@ -36,6 +36,8 @@ void enable_ocotp_clk(unsigned char enable);
 #ifdef CONFIG_USB_EHCI_HCD
 void enable_usboh3_clk(unsigned char enable);
 #endif
+void enable_mipi_dsi_clk(unsigned char enable);
+void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq_in_khz);
 void init_clk_usdhc(u32 index);
 void clock_init(void);
 void hab_caam_clock_enable(unsigned char enable);
diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
index 3abb166ee5..de4e32903a 100644
--- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
@@ -67,6 +67,8 @@
 #define SIM1_PCC1_SLOT			(48)
 #define MMDC0_AIPS3_SLOT		(43)
 #define IOMUXC_DDR_AIPS3_SLOT		(45)
+#define DSI_AIPS3_SLOT			(41)
+#define LCDIF_AIPS3_SLOT		(42)
 
 #define LPI2C0_AIPS0_SLOT		(51)
 #define LPI2C1_AIPS0_SLOT		(52)
@@ -183,6 +185,10 @@
 #define USDHC0_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT)))
 #define USDHC1_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT)))
 
+#define LCDIF_RBASE	((AIPS3_BASE + (AIPS3_SLOT_SIZE * LCDIF_AIPS3_SLOT)))
+#define MXS_LCDIF_BASE	LCDIF_RBASE
+
+
 #define SNVS_BASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * SNVS_AIPS2_SLOT)))
 #define SNVS_LP_LPCR	(SNVS_BASE + 0x38)
 
@@ -966,6 +972,7 @@
 #define IOMUXC_BASE_ADDR		IOMUXC1_RBASE
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/mach-imx/regs-lcdif.h>
 
 #include <asm/types.h>
 
diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c
index 6830b89608..a70d5957f6 100644
--- a/arch/arm/mach-imx/mx7ulp/clock.c
+++ b/arch/arm/mach-imx/mx7ulp/clock.c
@@ -326,6 +326,88 @@ void hab_caam_clock_enable(unsigned char enable)
 }
 #endif
 
+void enable_mipi_dsi_clk(unsigned char enable)
+{
+	if (enable) {
+		pcc_clock_enable(PER_CLK_DSI, false);
+
+		/* mipi dsi escape clock range is 40-80Mhz, we expect to set it to about 60 Mhz
+		 * To avoid PCD issue, we select parent clock with lowest frequency
+		 * NIC1_CLK = 1584000khz, frac = 1, div = 5,  output = 63.360Mhz
+		 */
+		pcc_clock_sel(PER_CLK_DSI, SCG_NIC1_CLK);
+		pcc_clock_div_config(PER_CLK_DSI, 1, 5);
+
+		pcc_clock_enable(PER_CLK_DSI, true);
+	} else {
+		pcc_clock_enable(PER_CLK_DSI, false);
+	}
+}
+
+void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq_in_khz)
+{
+	/* Scan the parent clock to find best fit clock, whose generate actual frequence <= freq
+	*   Otherwise, the higher actual freq may introduce some problem
+	*   1. The real frequency exceeds max framerate that screen supports
+	*   2. The DSI PHY clock depends on the lcdif clock, so the higher lcdif clock may violate
+	*       DSI PHY clock requirement
+	*/
+	u8 pcd, best_pcd = 0;
+	u32 parent, frac, rate, parent_rate;
+	u32 best_parent = 0, best_frac = 0, best = 0;
+
+	static enum scg_clk clksrc_plat[] = {
+		SCG_NIC1_BUS_CLK,
+		SCG_NIC1_CLK,
+		SCG_DDR_CLK,
+		SCG_APLL_PFD2_CLK,
+		SCG_APLL_PFD1_CLK,
+		SCG_APLL_PFD0_CLK,
+		USB_PLL_OUT,
+	};
+
+	pcc_clock_enable(PER_CLK_LCDIF, false);
+
+	for (parent = 0; parent < ARRAY_SIZE(clksrc_plat); parent++) {
+		parent_rate = scg_clk_get_rate(clksrc_plat[parent]);
+		if (!parent_rate)
+			continue;
+
+		parent_rate = parent_rate / 1000; /* Change to khz*/
+
+		for (pcd = 0; pcd < 8; pcd++) {
+			for (frac = 0; frac < 2; frac++) {
+				if (pcd == 0 && frac == 1)
+					continue;
+
+				rate = parent_rate * (frac + 1) / (pcd + 1);
+				if (rate > freq_in_khz)
+					continue;
+
+				if (best == 0 || rate > best) {
+					best = rate;
+					best_parent = parent;
+					best_frac = frac;
+					best_pcd = pcd;
+				}
+			}
+		}
+	}
+
+	if (best == 0) {
+		printf("Can't find parent clock for LCDIF, target freq: %u\n", freq_in_khz);
+		return;
+	}
+
+	debug("LCD target rate %ukhz, best rate %ukhz, frac %u, pcd %u, best_parent %u\n",
+	      freq_in_khz, best, best_frac, best_pcd, best_parent);
+
+	pcc_clock_sel(PER_CLK_LCDIF, clksrc_plat[best_parent]);
+	pcc_clock_div_config(PER_CLK_LCDIF, best_frac, best_pcd + 1);
+	pcc_clock_enable(PER_CLK_LCDIF, true);
+}
+
+
 #ifndef CONFIG_SPL_BUILD
 /*
  * Dump some core clockes.