diff options
| author | Clark Wang <xiaoning.wang@nxp.com> | 2020-09-11 15:12:36 +0800 |
|---|---|---|
| committer | Clark Wang <xiaoning.wang@nxp.com> | 2020-09-15 10:58:46 +0800 |
| commit | 132ea95f15f3dcf3408d70eb7879533b412cd521 (patch) | |
| tree | 637274976e4b73597d973dfb4f5ef6248f89dbae /arch | |
| parent | dd6a4a23ac8a774f576bacd6a67ca4d56307df26 (diff) | |
MLK-24766-3 imx7ulp-clk: add lpspi clk enable function
Enable LPSPI2-3 clock enable and get functions.
Please note that the lpspi's alias should only be set as same as its
module number.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-mx7ulp/clock.h | 6 | ||||
| -rw-r--r-- | arch/arm/mach-imx/mx7ulp/clock.c | 38 |
2 files changed, 43 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h index ccd6a9a0a3..a700d8b87d 100644 --- a/arch/arm/include/asm/arch-mx7ulp/clock.h +++ b/arch/arm/include/asm/arch-mx7ulp/clock.h @@ -16,7 +16,7 @@ enum mxc_clock { MXC_AHB_CLK, MXC_IPG_CLK, MXC_UART_CLK, - MXC_CSPI_CLK, + MXC_LPSPI_CLK, MXC_AXI_CLK, MXC_DDR_CLK, MXC_ESDHC_CLK, @@ -30,6 +30,10 @@ u32 get_lpuart_clk(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); u32 imx_get_i2cclk(unsigned i2c_num); #endif +#ifdef CONFIG_FSL_LPSPI +int enable_lpspi_clk(unsigned char enable, unsigned spi_num); +u32 imx_get_spiclk(unsigned spi_num); +#endif #ifdef CONFIG_MXC_OCOTP void enable_ocotp_clk(unsigned char enable); #endif diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index a70d5957f6..4acd887bdb 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -114,6 +114,42 @@ u32 imx_get_i2cclk(unsigned i2c_num) } #endif +#ifdef CONFIG_FSL_LPSPI +int enable_lpspi_clk(unsigned char enable, unsigned spi_num) +{ + /* Set parent to FIRC DIV2 clock */ + const enum pcc_clk lpspi_pcc_clks[] = { + PER_CLK_LPSPI2, + PER_CLK_LPSPI3, + }; + + if (spi_num < 2 || spi_num > 3) + return -EINVAL; + + if (enable) { + pcc_clock_enable(lpspi_pcc_clks[spi_num - 2], false); + pcc_clock_sel(lpspi_pcc_clks[spi_num - 2], SCG_FIRC_DIV2_CLK); + pcc_clock_enable(lpspi_pcc_clks[spi_num - 2], true); + } else { + pcc_clock_enable(lpspi_pcc_clks[spi_num - 2], false); + } + return 0; +} + +u32 imx_get_spiclk(unsigned spi_num) +{ + const enum pcc_clk lpspi_pcc_clks[] = { + PER_CLK_LPSPI2, + PER_CLK_LPSPI3, + }; + + if (spi_num < 2 || spi_num > 3) + return 0; + + return pcc_clock_get_rate(lpspi_pcc_clks[spi_num - 2]); +} +#endif + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { @@ -127,6 +163,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_ipg_clk(); case MXC_I2C_CLK: return pcc_clock_get_rate(PER_CLK_LPI2C4); + case MXC_LPSPI_CLK: + return pcc_clock_get_rate(PER_CLK_LPSPI3); case MXC_UART_CLK: return get_lpuart_clk(); case MXC_ESDHC_CLK: |