diff options
| author | Lars Povlsen <lars.povlsen@microchip.com> | 2018-12-20 09:56:03 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2019-01-16 13:56:43 +0100 |
| commit | e58031acdc84bbd3c2d22fab4455a0f079f936a0 (patch) | |
| tree | 0c0ac2192a58e8110e6e8a891edaf4cf03196d37 /arch | |
| parent | 3098ade229af721c8b64b423e2e11f5896b45710 (diff) | |
mips: mscc: Add generic GPIO control utility function
The GPIO control function can be used for controlling alternate
functions associated with a GPIO.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/mach-mscc/Makefile | 2 | ||||
| -rw-r--r-- | arch/mips/mach-mscc/gpio.c | 33 | ||||
| -rw-r--r-- | arch/mips/mach-mscc/include/mach/common.h | 2 | ||||
| -rw-r--r-- | arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h | 2 | ||||
| -rw-r--r-- | arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h | 2 |
5 files changed, 40 insertions, 1 deletions
diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile index 300c88b5cd0..44538b7118b 100644 --- a/arch/mips/mach-mscc/Makefile +++ b/arch/mips/mach-mscc/Makefile @@ -2,5 +2,5 @@ CFLAGS_cpu.o += -finline-limit=64000 -obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o +obj-y += cpu.o dram.o reset.o phy.o gpio.o lowlevel_init.o obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o diff --git a/arch/mips/mach-mscc/gpio.c b/arch/mips/mach-mscc/gpio.c new file mode 100644 index 00000000000..5e3a53372d9 --- /dev/null +++ b/arch/mips/mach-mscc/gpio.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include <common.h> +#include <asm/io.h> + +void mscc_gpio_set_alternate(int gpio, int mode) +{ + u32 mask = BIT(gpio); + u32 val0, val1; + + val0 = readl(BASE_DEVCPU_GCB + GPIO_ALT(0)); + val1 = readl(BASE_DEVCPU_GCB + GPIO_ALT(1)); + + if (mode == 1) { + val0 |= mask; + val1 &= ~mask; + } else if (mode == 2) { + val0 &= ~mask; + val1 |= mask; + } else if (mode == 3) { + val0 |= mask; + val1 |= mask; + } else { + val0 &= ~mask; + val1 &= ~mask; + } + + writel(val0, BASE_DEVCPU_GCB + GPIO_ALT(0)); + writel(val1, BASE_DEVCPU_GCB + GPIO_ALT(1)); +} diff --git a/arch/mips/mach-mscc/include/mach/common.h b/arch/mips/mach-mscc/include/mach/common.h index 92a055561eb..d18ae78bfd1 100644 --- a/arch/mips/mach-mscc/include/mach/common.h +++ b/arch/mips/mach-mscc/include/mach/common.h @@ -45,4 +45,6 @@ int mscc_phy_wr(u32 miim_controller, u8 addr, u16 value); +void mscc_gpio_set_alternate(int gpio, int mode); + #endif /* __ASM_MACH_COMMON_H */ diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h index 8c0b612325e..a06cf819b09 100644 --- a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h @@ -11,4 +11,6 @@ #define PERF_SOFT_RST_SOFT_SWC_RST BIT(1) #define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0) +#define GPIO_ALT(x) (0x88 + 4 * (x)) + #endif diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h index f8aa97ba267..d3a76412e2e 100644 --- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h @@ -18,4 +18,6 @@ #define PERF_GPIO_OE 0x44 +#define GPIO_ALT(x) (0x54 + 4 * (x)) + #endif |