diff options
| author | Kenneth Johansson <kenneth@southpole.se> | 2008-07-12 13:18:34 -0600 |
|---|---|---|
| committer | John Rigby <jrigby@freescale.com> | 2008-07-12 13:34:15 -0600 |
| commit | f889265753ddf4465d9d580827bb9289bfac55d6 (patch) | |
| tree | 13d14481f9fa5dccf61bb628ec4d1fe319ab0b9c /board/ads5121/ads5121_diu.c | |
| parent | b60b8573875e650e4c69be667bfc88d3ed474a7c (diff) | |
fix DIU for small screens
The DIU_DIV register is 8 bit not 5 bit. This prevented large DIV values
so it was not possible to set a slow pixel clock and thus prevented
display on small screens.
Signed-off-by: Kenneth Johansson <kenneth@southpole.se>
Acked-by: John Rigby <jrigby@freescale.com>
Diffstat (limited to 'board/ads5121/ads5121_diu.c')
| -rw-r--r-- | board/ads5121/ads5121_diu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/ads5121/ads5121_diu.c b/board/ads5121/ads5121_diu.c index 87cf0cbbe91..26628d3eb54 100644 --- a/board/ads5121/ads5121_diu.c +++ b/board/ads5121/ads5121_diu.c @@ -57,7 +57,7 @@ void diu_set_pixel_clock(unsigned int pixclock) /* Modify PXCLK in GUTS CLKDVDR */ debug("DIU: Current value of CLKDVDR = 0x%08x\n", *clkdvdr); temp = *clkdvdr & 0xFFFFFF00; - *clkdvdr = temp | (pixval & 0x1F); + *clkdvdr = temp | (pixval & 0xFF); debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr); } |