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authorHeiko Schocher <hs@denx.de>2015-09-25 12:31:49 +0200
committerStefano Babic <sbabic@denx.de>2015-10-30 15:08:55 +0100
commitc39fcad7806f18763e2cb4d244863ccd024540c0 (patch)
treed07acadc6c7d6bf8cc0883f14670ee8c413b5fbb /board/aristainetos
parentd62f2f8cdfd7ee9bd1e61fa1e71723340f870071 (diff)
arm, imx6, aristainetos2: set gpr register after reset
setting the gpr 1,8 and 12 registers to a fix value. This is needed because after a WDT reset, this registers are not correct resettet, and prevent linux from booting again. Signed-off-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'board/aristainetos')
-rw-r--r--board/aristainetos/aristainetos-v2.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/board/aristainetos/aristainetos-v2.c b/board/aristainetos/aristainetos-v2.c
index 49dbd2e4972..fa4b4d2c153 100644
--- a/board/aristainetos/aristainetos-v2.c
+++ b/board/aristainetos/aristainetos-v2.c
@@ -580,6 +580,21 @@ static void setup_iomux_gpio(void)
imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
}
+static void set_gpr_register(void)
+{
+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
+ IOMUXC_GPR1_EXC_MON_SLVE |
+ (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
+ IOMUXC_GPR1_ACT_CS0,
+ &iomuxc_regs->gpr[1]);
+ writel(0x0, &iomuxc_regs->gpr[8]);
+ writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
+ IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
+ &iomuxc_regs->gpr[12]);
+}
+
int board_early_init_f(void)
{
setup_iomux_uart();
@@ -588,6 +603,7 @@ int board_early_init_f(void)
gpio_direction_output(SOFT_RESET_GPIO, 1);
gpio_direction_output(SD2_DRIVER_ENABLE, 1);
setup_display();
+ set_gpr_register();
return 0;
}