Blackfin: bf537-stamp: post: update old MMR style macros

The old MMR defines are being scrubbed, so convert the driver to use the
new standard helper macros.

For the GPIO MMR usage, convert to the new GPIO framework.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

1 files changed, 27 insertions, 27 deletions

diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c
index 4daea627ef..49022dc930 100644
--- a/board/bf537-stamp/post-memory.c
+++ b/board/bf537-stamp/post-memory.c
@@ -97,19 +97,19 @@ void post_init_uart(int sclk)
 	for (divisor = 0; sclk > 0; divisor++)
 		sclk -= 57600 * 16;
 
-	*pPORTF_FER = 0x000F;
-	*pPORTH_FER = 0xFFFF;
+	bfin_write_PORTF_FER(0x000F);
+	bfin_write_PORTH_FER(0xFFFF);
 
-	*pUART_GCTL = 0x00;
-	*pUART_LCR = 0x83;
+	bfin_write_UART_GCTL(0x00);
+	bfin_write_UART_LCR(0x83);
 	SSYNC();
-	*pUART_DLL = (divisor & 0xFF);
+	bfin_write_UART_DLL(divisor & 0xFF);
 	SSYNC();
-	*pUART_DLH = ((divisor >> 8) & 0xFF);
+	bfin_write_UART_DLH((divisor >> 8) & 0xFF);
 	SSYNC();
-	*pUART_LCR = 0x03;
+	bfin_write_UART_LCR(0x03);
 	SSYNC();
-	*pUART_GCTL = 0x01;
+	bfin_write_UART_GCTL(0x01);
 	SSYNC();
 }
 
@@ -121,8 +121,8 @@ void post_out_buff(char *buff)
 		;
 	i = 0;
 	while ((buff[i] != '\0') && (i != 100)) {
-		while (!(*pUART_LSR & 0x20)) ;
-		*pUART_THR = buff[i];
+		while (!(bfin_read_pUART_LSR() & 0x20)) ;
+		bfin_write_UART_THR(buff[i]);
 		SSYNC();
 		i++;
 	}
@@ -138,15 +138,15 @@ int post_key_pressed(void)
 	int i, n;
 	unsigned short value;
 
-	*pPORTF_FER &= ~PF5;
-	*pPORTFIO_DIR &= ~PF5;
-	*pPORTFIO_INEN |= PF5;
+	bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF5);
+	bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~PF5);
+	bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | PF5);
 	SSYNC();
 
 	post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
 	for (i = 0; i < KEY_LOOP; i++) {
-		value = *pPORTFIO & PF5;
-		if (*pUART0_RBR == 0x0D) {
+		value = bfin_read_PORTFIO() & PF5;
+		if (bfin_read_UART0_RBR() == 0x0D) {
 			value = 0;
 			goto key_pressed;
 		}
@@ -158,8 +158,8 @@ int post_key_pressed(void)
 	post_out_buff("\b2\0");
 
 	for (i = 0; i < KEY_LOOP; i++) {
-		value = *pPORTFIO & PF5;
-		if (*pUART0_RBR == 0x0D) {
+		value = bfin_read_PORTFIO() & PF5;
+		if (bfin_read_UART0_RBR() == 0x0D) {
 			value = 0;
 			goto key_pressed;
 		}
@@ -171,8 +171,8 @@ int post_key_pressed(void)
 	post_out_buff("\b1\0");
 
 	for (i = 0; i < KEY_LOOP; i++) {
-		value = *pPORTFIO & PF5;
-		if (*pUART0_RBR == 0x0D) {
+		value = bfin_read_PORTFIO() & PF5;
+		if (bfin_read_UART0_RBR() == 0x0D) {
 			value = 0;
 			goto key_pressed;
 		}
@@ -193,13 +193,13 @@ int post_key_pressed(void)
 void post_init_pll(int mult, int div)
 {
 
-	*pSIC_IWR = 0x01;
-	*pPLL_CTL = (mult << 9);
-	*pPLL_DIV = div;
+	bfin_write_SIC_IWR(0x01);
+	bfin_write_PLL_CTL((mult << 9));
+	bfin_write_PLL_DIV(div);
 	asm("CLI R2;");
 	asm("IDLE;");
 	asm("STI R2;");
-	while (!(*pPLL_STAT & 0x20)) ;
+	while (!(bfin_read_PLL_STAT() & 0x20)) ;
 }
 
 int post_init_sdram(int sclk)
@@ -302,15 +302,15 @@ int post_init_sdram(int sclk)
 
 	SSYNC();
 
-	*pEBIU_SDGCTL |= 0x1000000;
+	bfin_write_EBIU_SDGCTL(bfin_write_EBIU_SDGCTL() | 0x1000000);
 	/* Set the SDRAM Refresh Rate control register based on SSCLK value */
-	*pEBIU_SDRRC = mem_SDRRC;
+	bfin_write_EBIU_SDRRC(mem_SDRRC);
 
 	/* SDRAM Memory Bank Control Register */
-	*pEBIU_SDBCTL = mem_SDBCTL;
+	bfin_write_EBIU_SDBCTL(mem_SDBCTL);
 
 	/* SDRAM Memory Global Control Register */
-	*pEBIU_SDGCTL = mem_SDGCTL;
+	bfin_write_EBIU_SDGCTL(mem_SDGCTL);
 	SSYNC();
 	return mem_SDRRC;
 }