diff options
| author | Wolfgang Denk <wd@denx.de> | 2008-10-19 02:35:50 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-21 11:25:39 +0200 |
| commit | 8ed44d91c8122d00368523b0b746691c895d3b3c (patch) | |
| tree | 7e2ff620c5b378aa82208c3e7a99e2a56570ddb7 /board/cray | |
| parent | 08ef89ecd174969b3544f3f0c7cd1de3c57f737b (diff) | |
Cleanup: fix "MHz" spelling
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'board/cray')
| -rw-r--r-- | board/cray/L1/L1.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c index 2babd2d358a..1c82bdf1251 100644 --- a/board/cray/L1/L1.c +++ b/board/cray/L1/L1.c @@ -205,13 +205,13 @@ static void init_sdram (void) /* To set the appropriate timings, we need to know the SDRAM speed. */ /* We can use the PLB speed since the SDRAM speed is the same as */ /* the PLB speed. The PLB speed is the FBK divider times the */ -/* 405GP reference clock, which on the L1 is 25Mhz. */ -/* Thus, if FBK div is 2, SDRAM is 50Mhz; if FBK div is 3, SDRAM is */ -/* 150Mhz; if FBK is 3, SDRAM is 150Mhz. */ +/* 405GP reference clock, which on the L1 is 25MHz. */ +/* Thus, if FBK div is 2, SDRAM is 50MHz; if FBK div is 3, SDRAM is */ +/* 150MHz; if FBK is 3, SDRAM is 150MHz. */ /* divisor = ((mfdcr(strap)>> 28) & 0x3); */ -/* write SDRAM timing for 100Mhz. */ +/* write SDRAM timing for 100MHz. */ mtdcr (memcfga, mem_sdtr1); mtdcr (memcfgd, 0x0086400D); |