diff options
| author | Trent Piepho <tpiepho@freescale.com> | 2008-12-03 15:16:34 -0800 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-12-19 18:20:25 -0600 |
| commit | a5d212a263c58cc746481bf1fc878510533ce7d6 (patch) | |
| tree | eb08c782227ec1399e96eb6dc082db2123262e41 /board/freescale/mpc8568mds | |
| parent | 58ec4866ed916c7e422f5107bb27b0822084728e (diff) | |
mpc8xxx: LCRR[CLKDIV] is sometimes five bits
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.
In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It
should be safe as the fifth bit was defined as reserved and set to 0.
Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
Diffstat (limited to 'board/freescale/mpc8568mds')
| -rw-r--r-- | board/freescale/mpc8568mds/mpc8568mds.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index bc93be80fcb..7a23b338a59 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -188,7 +188,7 @@ local_bus_init(void) sys_info_t sysinfo; get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & 0x0f) * 2; + clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; |