ppc_4xx: Apply new HW register names

Modify all existing *.c files to use the new register names
as seen in the AMCC manuals.

Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>

2 files changed, 27 insertions, 27 deletions

diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c
index 7cc1bf26783..90dbe52aa28 100644
--- a/board/gdsys/gdppc440etx/gdppc440etx.c
+++ b/board/gdsys/gdppc440etx/gdppc440etx.c
@@ -239,22 +239,22 @@ void pci_target_init(struct pci_controller *hose)
 	 *   Use byte reversed out routines to handle endianess.
 	 * Make this region non-prefetchable.
 	 */
-	out32r(PCIX0_PMM0MA, 0x00000000); 	/* disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
-	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
-	out32r(PCIX0_PMM0PCIHA, 0x00000000);
-	out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */
-
-	out32r(PCIX0_PMM1MA, 0x00000000);	/* disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
-	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
-	out32r(PCIX0_PMM1PCIHA, 0x00000000);
-	out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */
-
-	out32r(PCIX0_PTM1MS, 0x00000001);
-	out32r(PCIX0_PTM1LA, 0);
-	out32r(PCIX0_PTM2MS, 0);
-	out32r(PCIX0_PTM2LA, 0);
+	out32r(PCIL0_PMM0MA, 0x00000000); 	/* disabled b4 setting */
+	out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
+	out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
+	out32r(PCIL0_PMM0PCIHA, 0x00000000);
+	out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */
+
+	out32r(PCIL0_PMM1MA, 0x00000000);	/* disabled b4 setting */
+	out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
+	out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
+	out32r(PCIL0_PMM1PCIHA, 0x00000000);
+	out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */
+
+	out32r(PCIL0_PTM1MS, 0x00000001);
+	out32r(PCIL0_PTM1LA, 0);
+	out32r(PCIL0_PTM2MS, 0);
+	out32r(PCIL0_PTM2LA, 0);
 
 	/*
 	 * Set up Configuration registers
diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c
index 2cd2e6d4503..b42e90853f4 100644
--- a/board/gdsys/intip/intip.c
+++ b/board/gdsys/intip/intip.c
@@ -154,27 +154,27 @@ void pci_target_init(struct pci_controller *hose)
 	/*
 	 * Disable everything
 	 */
-	out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
-	out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
-	out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
-	out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
+	out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
+	out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
+	out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
+	out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
 
 	/*
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 	 * strapping options to not support sizes such as 128/256 MB.
 	 */
-	out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-	out_le32((void *)PCIX0_PIM0LAH, 0);
-	out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
-	out_le32((void *)PCIX0_BAR0, 0);
+	out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+	out_le32((void *)PCIL0_PIM0LAH, 0);
+	out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
+	out_le32((void *)PCIL0_BAR0, 0);
 
 	/*
 	 * Program the board's subsystem id/vendor id
 	 */
-	out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-	out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+	out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
-	out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+	out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
 }
 #endif	/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */