diff options
| author | Stefan Roese <sr@denx.de> | 2010-04-14 13:57:18 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2010-04-19 15:29:03 +0200 |
| commit | cf6eb6da433179674571f9370566b1ec8989a41a (patch) | |
| tree | fc0ad7161d7146154026fa789a97dd2c047c61a7 /board/korat | |
| parent | 2a72e9ed18d2164eb7fe569119342eb631b568da (diff) | |
ppc4xx: TLB init file cleanup
This patch adds new macros, with frequently used combinations of the
4xx TLB access control and storage attibutes. Additionally the 4xx init.S
files are updated to make use of these new macros. Resulting in easier
to read TLB definitions.
Additionally some init.S files are updated to use the mmu header for the
TLB defines, instead of defining their own macros.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/korat')
| -rw-r--r-- | board/korat/init.S | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/board/korat/init.S b/board/korat/init.S index c725bbbb44d..bfc6bc15253 100644 --- a/board/korat/init.S +++ b/board/korat/init.S @@ -43,7 +43,7 @@ tlbtab: * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ - tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_R|AC_W|AC_X|SA_G ) + tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_RWX | SA_G ) /* * TLB entries for SDRAM are not needed on this platform. They are @@ -53,37 +53,37 @@ tlbtab: #ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, - AC_R|AC_W|AC_X|SA_G ) + AC_RWX | SA_G ) #endif /* TLB-entry for PCI Memory */ tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x00000000, SZ_256M, - CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_R|AC_W|SA_G|SA_I ) + CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_RW | SA_IG ) tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x10000000, SZ_256M, - CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_R|AC_W|SA_G|SA_I ) + CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_RW | SA_IG ) tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x20000000, SZ_256M, - CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_R|AC_W|SA_G|SA_I ) + CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_RW | SA_IG ) tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x30000000, SZ_256M, - CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_R|AC_W|SA_G|SA_I ) + CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_RW | SA_IG ) /* TLB-entry for EBC */ - tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RW | SA_IG ) /* TLB-entry for Internal Registers & OCM */ /* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */ - tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_R|AC_W|AC_X|SA_I ) + tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_RWX | SA_I ) /*TLB-entry PCI registers*/ - tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RW | SA_IG ) /* TLB-entry for peripherals */ - tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RW | SA_IG) /* TLB-entry PCI IO Space - from sr@denx.de */ - tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RW | SA_IG) tlbtab_end |