rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

3 files changed, 77 insertions, 77 deletions

diff --git a/board/lwmon/flash.c b/board/lwmon/flash.c
index 8d98545a531..f71cc242f7b 100644
--- a/board/lwmon/flash.c
+++ b/board/lwmon/flash.c
@@ -28,7 +28,7 @@
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -40,14 +40,14 @@
 
 /*---------------------------------------------------------------------*/
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
  */
 static ulong flash_get_size (vu_long *addr, flash_info_t *info);
 static int write_data (flash_info_t *info, ulong dest, ulong data);
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 static int write_data_buf (flash_info_t * info, ulong dest, uchar * cp, int len);
 #endif
 static void flash_get_offsets (ulong base, flash_info_t *info);
@@ -57,13 +57,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info);
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0, size_b1;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -108,25 +108,25 @@ unsigned long flash_init (void)
 		memctl->memc_br1, memctl->memc_or1);
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = (-size_b0 & 0xFFFF8000) | CFG_OR_TIMING_FLASH |
+	memctl->memc_or0 = (-size_b0 & 0xFFFF8000) | CONFIG_SYS_OR_TIMING_FLASH |
 				OR_CSNT_SAM | OR_ACS_DIV1;
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V;
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V;
 
 	debug ("## BR0: 0x%08x    OR0: 0x%08x\n",
 		memctl->memc_br0, memctl->memc_or0);
 
 	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	flash_info[0].size = size_b0;
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -139,27 +139,27 @@ unsigned long flash_init (void)
 #endif
 
 	if (size_b1) {
-		memctl->memc_or1 = (-size_b1 & 0xFFFF8000) | CFG_OR_TIMING_FLASH |
+		memctl->memc_or1 = (-size_b1 & 0xFFFF8000) | CONFIG_SYS_OR_TIMING_FLASH |
 					OR_CSNT_SAM | OR_ACS_DIV1;
-		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+		memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
 					BR_PS_32 | BR_V;
 
 		debug ("## BR1: 0x%08x    OR1: 0x%08x\n",
 			memctl->memc_br1, memctl->memc_or1);
 
 		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
 					  &flash_info[1]);
 
 		flash_info[1].size = size_b1;
 
-		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 			      &flash_info[1]);
 #endif
 
@@ -342,10 +342,10 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = 0x00FF00FF;		/* restore read mode */
@@ -409,7 +409,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 			udelay (1000);
 			/* This takes awfully long - up to 50 ms and more */
 			while (((status = *addr) & 0x00800080) != 0x00800080) {
-				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = 0x00FF00FF; /* reset to read mode */
 					return 1;
@@ -435,7 +435,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 			udelay (1000);
 
 			while (((status = *addr) & 0x00800080) != 0x00800080) {
-				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = 0x00B000B0; /* suspend erase	  */
 					*addr = 0x00FF00FF; /* reset to read mode */
@@ -504,10 +504,10 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	/*
 	 * handle FLASH_WIDTH aligned part
 	 */
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 	while(cnt >= FLASH_WIDTH) {
-		i = CFG_FLASH_BUFFER_SIZE > cnt ?
-		    (cnt & ~(FLASH_WIDTH - 1)) : CFG_FLASH_BUFFER_SIZE;
+		i = CONFIG_SYS_FLASH_BUFFER_SIZE > cnt ?
+		    (cnt & ~(FLASH_WIDTH - 1)) : CONFIG_SYS_FLASH_BUFFER_SIZE;
 		if((rc = write_data_buf(info, wp, src,i)) != 0)
 			return rc;
 		wp += i;
@@ -526,7 +526,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 		wp  += FLASH_WIDTH;
 		cnt -= FLASH_WIDTH;
 	}
-#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 
 	if (cnt == 0) {
 		return (0);
@@ -594,7 +594,7 @@ static int write_data (flash_info_t *info, ulong dest, ulong data)
 	if (flag)
 		enable_interrupts();
 
-	if (flash_status_check(addr, CFG_FLASH_WRITE_TOUT, "write") != 0) {
+	if (flash_status_check(addr, CONFIG_SYS_FLASH_WRITE_TOUT, "write") != 0) {
 		return (1);
 	}
 
@@ -603,7 +603,7 @@ static int write_data (flash_info_t *info, ulong dest, ulong data)
 	return (0);
 }
 
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 /*-----------------------------------------------------------------------
  * Write a buffer to Flash, returns:
  * 0 - OK
@@ -627,7 +627,7 @@ static int write_data_buf(flash_info_t * info, ulong dest, uchar * cp, int len)
 	*addr = 0x00500050;		/* clear status */
 	*addr = 0x00e800e8;		/* write buffer */
 
-	if((retcode = flash_status_check(addr, CFG_FLASH_BUFFER_WRITE_TOUT,
+	if((retcode = flash_status_check(addr, CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT,
 					 "write to buffer")) == 0) {
 		cnt = len / FLASH_WIDTH;
 		*addr = (cnt-1) | ((cnt-1) << 16);
@@ -635,14 +635,14 @@ static int write_data_buf(flash_info_t * info, ulong dest, uchar * cp, int len)
 			*dst++ = *src++;
 		}
 		*addr = 0x00d000d0;		/* write buffer confirm */
-		retcode = flash_status_check(addr, CFG_FLASH_BUFFER_WRITE_TOUT,
+		retcode = flash_status_check(addr, CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT,
 						 "buffer write");
 	}
 	*addr = 0x00FF00FF;	/* restore read mode */
 	*addr = 0x00500050;	/* clear status */
 	return retcode;
 }
-#endif /* CFG_USE_FLASH_BUFFER_WRITE */
+#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
 
 /*-----------------------------------------------------------------------
  */
diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c
index 4a2d8e4a4fd..aadd2540e84 100644
--- a/board/lwmon/lwmon.c
+++ b/board/lwmon/lwmon.c
@@ -66,7 +66,7 @@ extern void disable_putc(void);
  */
 const uint sdram_table[] =
 {
-#if defined(CFG_MEMORY_75) || defined(CFG_MEMORY_8E)
+#if defined(CONFIG_SYS_MEMORY_75) || defined(CONFIG_SYS_MEMORY_8E)
 	/*
 	 * Single Read. (Offset 0 in UPM RAM)
 	 */
@@ -114,7 +114,7 @@ const uint sdram_table[] =
 	0x7FFFFC07, /* last */
 		    0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
 #endif
-#ifdef CFG_MEMORY_7E
+#ifdef CONFIG_SYS_MEMORY_7E
 	/*
 	 * Single Read. (Offset 0 in UPM RAM)
 	 */
@@ -211,7 +211,7 @@ V* Verification: dzu@denx.de
  ***********************************************************************/
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immr->im_memctl;
 	long int size_b0;
 	long int size8, size9;
@@ -222,19 +222,19 @@ phys_size_t initdram (int board_type)
 	 */
 	upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
 
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	/* burst length=4, burst type=sequential, CAS latency=2 */
-	memctl->memc_mar = CFG_MAR;
+	memctl->memc_mar = CONFIG_SYS_MAR;
 
 	/*
 	 * Map controller bank 3 to the SDRAM bank at preliminary address.
 	 */
-	memctl->memc_or3 = CFG_OR3_PRELIM;
-	memctl->memc_br3 = CFG_BR3_PRELIM;
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 
 	/* initialize memory address register */
-	memctl->memc_mamr = CFG_MAMR_8COL;	/* refresh not enabled yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;	/* refresh not enabled yet */
 
 	/* mode initialization (offset 5) */
 	udelay (200);				/* 0x80006105 */
@@ -268,22 +268,22 @@ phys_size_t initdram (int board_type)
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
 
 	udelay (1000);
 
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
 
 	if (size8 < size9) {		/* leave configuration at 9 columns */
 		size_b0 = size9;
-		memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTAE;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_9COL | MAMR_PTAE;
 		udelay (500);
 	} else {			/* back to 8 columns            */
 		size_b0 = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL | MAMR_PTAE;
 		udelay (500);
 	}
 
@@ -293,7 +293,7 @@ phys_size_t initdram (int board_type)
 
 	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) |
 			OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
-	memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 	udelay (1000);
 
 	return (size_b0);
@@ -327,7 +327,7 @@ V* Verification: dzu@denx.de
  ***********************************************************************/
 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immr->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
@@ -359,7 +359,7 @@ V* Verification: dzu@denx.de
  ***********************************************************************/
 int board_early_init_f (void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 	/* Disable Ethernet TENA on Port B
 	 * Necessary because of pull up in COM3 port.
@@ -437,7 +437,7 @@ void reset_phy (void)
 
 /* maximum number of "magic" key codes that can be assigned */
 
-static uchar kbd_addr = CFG_I2C_KEYBD_ADDR;
+static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
 
 static uchar *key_match (uchar *);
 
@@ -481,7 +481,7 @@ static void kbd_init (void)
 	uchar val, errcd;
 	int i;
 
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	gd->kbd_status = 0;
 
@@ -862,7 +862,7 @@ int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	int i;
 
 #if 0 /* Done in kbd_init */
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
 	/* Read keys */
@@ -887,7 +887,7 @@ U_BOOT_CMD(
 );
 
 /* Read and set LSB switch */
-#define CFG_PC_TXD1_ENA		0x0008		/* PC.12 */
+#define CONFIG_SYS_PC_TXD1_ENA		0x0008		/* PC.12 */
 
 /***********************************************************************
 F* Function:     int do_lsb (cmd_tbl_t *cmdtp, int flag,
@@ -920,7 +920,7 @@ V* Verification: dzu@denx.de
 int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	uchar val;
-	immap_t *immr = (immap_t *) CFG_IMMR;
+	immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 	switch (argc) {
 	case 1:					/* lsb - print setting */
@@ -932,14 +932,14 @@ int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 		if (strcmp (argv[1], "on") == 0) {
 			val |= 0x20;
-			immr->im_ioport.iop_pcpar &= ~(CFG_PC_TXD1_ENA);
-			immr->im_ioport.iop_pcdat |= CFG_PC_TXD1_ENA;
-			immr->im_ioport.iop_pcdir |= CFG_PC_TXD1_ENA;
+			immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_TXD1_ENA);
+			immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_TXD1_ENA;
+			immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_TXD1_ENA;
 		} else if (strcmp (argv[1], "off") == 0) {
 			val &= ~0x20;
-			immr->im_ioport.iop_pcpar &= ~(CFG_PC_TXD1_ENA);
-			immr->im_ioport.iop_pcdat &= ~(CFG_PC_TXD1_ENA);
-			immr->im_ioport.iop_pcdir |= CFG_PC_TXD1_ENA;
+			immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_TXD1_ENA);
+			immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_TXD1_ENA);
+			immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_TXD1_ENA;
 		} else {
 			break;
 		}
@@ -980,7 +980,7 @@ V* Verification: dzu@denx.de
  ***********************************************************************/
 uchar pic_read (uchar reg)
 {
-	return (i2c_reg_read (CFG_I2C_PICIO_ADDR, reg));
+	return (i2c_reg_read (CONFIG_SYS_I2C_PICIO_ADDR, reg));
 }
 
 /***********************************************************************
@@ -1001,7 +1001,7 @@ V* Verification: dzu@denx.de
  ***********************************************************************/
 void pic_write (uchar reg, uchar val)
 {
-	i2c_reg_write (CFG_I2C_PICIO_ADDR, reg, val);
+	i2c_reg_write (CONFIG_SYS_I2C_PICIO_ADDR, reg, val);
 }
 
 /*---------------------- Board Control Functions ----------------------*/
@@ -1022,7 +1022,7 @@ V* Verification: dzu@denx.de
 void board_poweroff (void)
 {
     /* Turn battery off */
-    ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~(1 << (31 - 13));
+    ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~(1 << (31 - 13));
 
     while (1);
 }
diff --git a/board/lwmon/pcmcia.c b/board/lwmon/pcmcia.c
index 8825bd9714e..ad2e60d590f 100644
--- a/board/lwmon/pcmcia.c
+++ b/board/lwmon/pcmcia.c
@@ -51,10 +51,10 @@ int pcmcia_hardware_enable(int slot)
 #endif
 	udelay(10000);
 
-	immap = (immap_t *)CFG_IMMR;
-	sysp  = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
-	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	sysp  = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
 
 	/*
 	 * Configure SIUMCR to enable PCMCIA port B
@@ -108,8 +108,8 @@ int pcmcia_hardware_enable(int slot)
 
 	/*  switch VCC on */
 	val |= MAX1604_OP_SUS | MAX1604_VCCBON;
-	i2c_init  (CFG_I2C_SPEED, CFG_I2C_SLAVE);
-	i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
+	i2c_init  (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1);
 
 	udelay(500000);
 
@@ -137,13 +137,13 @@ int pcmcia_hardware_disable(int slot)
 
 	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
 
-	immap = (immap_t *)CFG_IMMR;
-	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
 
 	/* remove all power, put output in high impedance state */
 	val  = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ;
-	i2c_init  (CFG_I2C_SPEED, CFG_I2C_SLAVE);
-	i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
+	i2c_init  (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1);
 
 	/* Configure PCMCIA General Control Register */
 	debug ("Disable PCMCIA buffers and assert RESET\n");
@@ -181,8 +181,8 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp)
 		" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
 		'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
 
-	immap = (immap_t *)CFG_IMMR;
-	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
 	/*
 	 * Disable PCMCIA buffers (isolate the interface)
 	 * and assert RESET signal
@@ -199,8 +199,8 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp)
 	 */
 	debug ("PCMCIA power OFF\n");
 	val  = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ;
-	i2c_init  (CFG_I2C_SPEED, CFG_I2C_SLAVE);
-	i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
+	i2c_init  (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1);
 
 	val = 0;
 	switch(vcc) {
@@ -216,7 +216,7 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp)
 		pcmp->pcmc_pipr,
 		(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
 
-	i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
+	i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1);
 	if (val) {
 		debug ("PCMCIA powered at %sV\n",
 			(val & MAX1604_VCC_35) ? "3.3" : "5.0");