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authorWolfgang Denk <wd@pollux.denx.de>2006-05-03 01:24:04 +0200
committerWolfgang Denk <wd@pollux.denx.de>2006-05-03 01:24:04 +0200
commit610cf3676ee7376e0a55419626a30414a7b20db2 (patch)
tree31d7b61fbfd7421441d44d0c47c580c722c69465 /board/nc650
parentda4849fb30db9ec2cb1ae0bafa7455b9c4cb87b3 (diff)
Coding Style cleanup
Diffstat (limited to 'board/nc650')
-rw-r--r--board/nc650/nand.c68
-rw-r--r--board/nc650/nc650.c12
2 files changed, 40 insertions, 40 deletions
diff --git a/board/nc650/nand.c b/board/nc650/nand.c
index f27e536e50..de54386ddd 100644
--- a/board/nc650/nand.c
+++ b/board/nc650/nand.c
@@ -37,22 +37,22 @@ static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
struct nand_chip *this = mtd->priv;
switch(cmd) {
- case NAND_CTL_SETCLE:
- this->IO_ADDR_W += 2;
- break;
- case NAND_CTL_CLRCLE:
- this->IO_ADDR_W -= 2;
- break;
- case NAND_CTL_SETALE:
- this->IO_ADDR_W += 1;
- break;
- case NAND_CTL_CLRALE:
- this->IO_ADDR_W -= 1;
- break;
- case NAND_CTL_SETNCE:
- case NAND_CTL_CLRNCE:
- /* nop */
- break;
+ case NAND_CTL_SETCLE:
+ this->IO_ADDR_W += 2;
+ break;
+ case NAND_CTL_CLRCLE:
+ this->IO_ADDR_W -= 2;
+ break;
+ case NAND_CTL_SETALE:
+ this->IO_ADDR_W += 1;
+ break;
+ case NAND_CTL_CLRALE:
+ this->IO_ADDR_W -= 1;
+ break;
+ case NAND_CTL_SETNCE:
+ case NAND_CTL_CLRNCE:
+ /* nop */
+ break;
}
}
#elif defined(CONFIG_IDS852_REV2)
@@ -64,24 +64,24 @@ static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
struct nand_chip *this = mtd->priv;
switch(cmd) {
- case NAND_CTL_SETCLE:
- *(((volatile __u8 *) this->IO_ADDR_W) + 0xa) = 0;
- break;
- case NAND_CTL_CLRCLE:
- *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
- break;
- case NAND_CTL_SETALE:
- *(((volatile __u8 *) this->IO_ADDR_W) + 0x9) = 0;
- break;
- case NAND_CTL_CLRALE:
- *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
- break;
- case NAND_CTL_SETNCE:
- *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
- break;
- case NAND_CTL_CLRNCE:
- *(((volatile __u8 *) this->IO_ADDR_W) + 0xc) = 0;
- break;
+ case NAND_CTL_SETCLE:
+ *(((volatile __u8 *) this->IO_ADDR_W) + 0xa) = 0;
+ break;
+ case NAND_CTL_CLRCLE:
+ *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
+ break;
+ case NAND_CTL_SETALE:
+ *(((volatile __u8 *) this->IO_ADDR_W) + 0x9) = 0;
+ break;
+ case NAND_CTL_CLRALE:
+ *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
+ break;
+ case NAND_CTL_SETNCE:
+ *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
+ break;
+ case NAND_CTL_CLRNCE:
+ *(((volatile __u8 *) this->IO_ADDR_W) + 0xc) = 0;
+ break;
}
}
#else
diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c
index c90ac9c955..8a6b5b00a9 100644
--- a/board/nc650/nc650.c
+++ b/board/nc650/nc650.c
@@ -265,8 +265,8 @@ int misc_init_r(void)
int iCompatMode = 0;
char *pParam = NULL;
char *envlb;
-
- /*
+
+ /*
First byte in CPLD read address space signals compatibility mode
0 - cp850
1 - kp852
@@ -274,9 +274,9 @@ int misc_init_r(void)
pParam = (char*)(CFG_CPLD_BASE);
if( *pParam != 0)
iCompatMode = 1;
-
+
if ( iCompatMode != 0) {
- /*
+ /*
In KP852 compatibility mode we have to write to
DPRAM as early as possible the binary coded
line config and board name.
@@ -288,7 +288,7 @@ int misc_init_r(void)
setenv( DPRAM_VARNAME, DEFAULT_LB);
envlb = DEFAULT_LB;
}
-
+
/* Status string */
printf("Mode: KP852(LB=%s)\n", envlb);
@@ -305,7 +305,7 @@ int misc_init_r(void)
} else {
puts("Mode: CP850\n");
}
-
+
return 0;
}
#endif