rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

5 files changed, 29 insertions, 29 deletions

diff --git a/board/netstal/hcu5/README.txt b/board/netstal/hcu5/README.txt
index 75c0dd7cd3e..f64987637a8 100644
--- a/board/netstal/hcu5/README.txt
+++ b/board/netstal/hcu5/README.txt
@@ -33,7 +33,7 @@ vector and start running.
 On-Chip Memory
 --------------
 
-0xe0010000- 0xe0013fff   CFG_OCM_BASE
+0xe0010000- 0xe0013fff   CONFIG_SYS_OCM_BASE
 The 440EPx includes a 16K on-chip memory that can be placed however
 software chooses.
 
@@ -149,7 +149,7 @@ From now on our copy is in RAM and we will run from there,
 	setup bd flash info
 	cpu_init_r: (cpu/ppc4xx/cpu_init.c)
 	    peripheral chip select in using defines like
-	    CFG_EBC_PB0A, CFG_EBC_PB0C from hcu5.h
+	    CONFIG_SYS_EBC_PB0A, CONFIG_SYS_EBC_PB0C from hcu5.h
 	mem_malloc_init
 	malloc_bin_reloc
 	spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM)
@@ -168,4 +168,4 @@ include/ppc440.h
 Drivers for serial etc are found under drivers/
 
 Don't ask question if you did not look at the README !!
-Most CFG_* and CONFIG_* switches are mentioned/explained there.
+Most CONFIG_SYS_* and CONFIG_* switches are mentioned/explained there.
diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
index f3428c2ad88..6f4ec296cb2 100644
--- a/board/netstal/hcu5/hcu5.c
+++ b/board/netstal/hcu5/hcu5.c
@@ -26,7 +26,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 #undef BOOTSTRAP_OPTION_A_ACTIVE
 
@@ -40,9 +40,9 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
 #define SDR0_ECID2		0x0082
 #define SDR0_ECID3		0x0083
 
-#define SYS_IO_ADDRESS			(CFG_CS_2 + 0x00e00000)
-#define SYS_SLOT_ADDRESS		(CFG_CPLD + 0x00400000)
-#define HCU_DIGITAL_IO_REGISTER	(CFG_CPLD + 0x0500000)
+#define SYS_IO_ADDRESS			(CONFIG_SYS_CS_2 + 0x00e00000)
+#define SYS_SLOT_ADDRESS		(CONFIG_SYS_CPLD + 0x00400000)
+#define HCU_DIGITAL_IO_REGISTER	(CONFIG_SYS_CPLD + 0x0500000)
 #define HCU_SW_INSTALL_REQUESTED	0x10
 
 /*
@@ -212,7 +212,7 @@ void hcu_led_set(u32 value)
  */
 u32 get_serial_number(void)
 {
-	u32 *serial = (u32 *)CFG_FLASH_BASE;
+	u32 *serial = (u32 *)CONFIG_SYS_FLASH_BASE;
 
 	if (in_be32(serial) == 0xffffffff)
 		return 0;
@@ -243,7 +243,7 @@ int misc_init_r(void)
 #ifdef CONFIG_ENV_IS_IN_FLASH
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[0]);
 
@@ -399,18 +399,18 @@ void pci_target_init(struct pci_controller *hose)
 	 */
 	/* PMM0 Mask/Attribute - disabled b4 setting */
 	out32r(PCIX0_PMM0MA, 0x00000000);
-	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
 	/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);
+	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
 	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	/* 512M + No prefetching, and enable region */
 	out32r(PCIX0_PMM0MA, 0xE0000001);
 
 	/* PMM0 Mask/Attribute - disabled b4 setting */
 	out32r(PCIX0_PMM1MA, 0x00000000);
-	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 Local Address */
 	/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);
+	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
 	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	/* 512M + No prefetching, and enable region */
 	out32r(PCIX0_PMM1MA, 0xE0000001);
@@ -426,8 +426,8 @@ void pci_target_init(struct pci_controller *hose)
 
 	/* Program the board's subsystem id/vendor id */
 	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-			      CFG_PCI_SUBSYS_VENDORID);
-	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+			      CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
 
 	/* Configure command register as bus master */
 	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
diff --git a/board/netstal/hcu5/init.S b/board/netstal/hcu5/init.S
index d73c861e668..05b5e389c20 100644
--- a/board/netstal/hcu5/init.S
+++ b/board/netstal/hcu5/init.S
@@ -42,7 +42,7 @@ tlbtab:
 	/* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */
 	tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
 	/* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */
-	tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0,
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0,
 		AC_R|AC_W|AC_X|SA_G|SA_I )
 
 	/* TLB#2: TLB-entry for EBC */
@@ -53,7 +53,7 @@ tlbtab:
 	 * off to use the speed up boot process. It is patched after relocation
 	 * to enable SA_I
 	 */
-	tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1,
+	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_1M, CONFIG_SYS_BOOT_BASE_ADDR, 1,
 		AC_R|AC_W|AC_X|SA_G)
 
 	/*
@@ -63,13 +63,13 @@ tlbtab:
 	 */
 
 	/* TLB#4: */
-	tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1,
+	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1,
 		AC_R|AC_W|SA_G|SA_I )
 	/* TLB#5: */
-	tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1,
+	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1,
 		AC_R|AC_W|SA_G|SA_I )
 	/* TLB#6: */
-	tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1,
+	tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1,
 		AC_R|AC_W|SA_G|SA_I )
 
 	/* TLB-entry for Internal Registers & OCM */
@@ -87,20 +87,20 @@ tlbtab:
 
 	/*		CAN */
 	/* TLB#10: */
-	tlbentry( CFG_CS_1, SZ_1K, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
 
 	/* TLB#11:  CPLD and IMC-Standard 32 MB */
-	tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
 
 	/* TLB#12: */
-	tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1,
+	tlbentry( CONFIG_SYS_CS_2 + 0x1000000, SZ_16M, CONFIG_SYS_CS_2 + 0x1000000, 1,
 		AC_R|AC_W|AC_X|SA_G|SA_I )
 
 	 /*		IMC-Fast 32 MB */
 	/* TLB#13: */
-	tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
 	/* TLB#14: */
-	tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3, 1,
+	tlbentry( CONFIG_SYS_CS_3 + 0x1000000, SZ_16M, CONFIG_SYS_CS_3, 1,
 		AC_R|AC_W|AC_X|SA_G|SA_I )
 
 	tlbtab_end
diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c
index e5df62ef7ad..f59bd7d1895 100644
--- a/board/netstal/hcu5/sdram.c
+++ b/board/netstal/hcu5/sdram.c
@@ -263,20 +263,20 @@ phys_size_t initdram (int board_type)
 	/*
 	 * Program tlb entries for this size (dynamic)
 	 */
-	remove_tlb(CFG_SDRAM_BASE, 256 << 20);
+	remove_tlb(CONFIG_SYS_SDRAM_BASE, 256 << 20);
 	program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE);
 
 	/*
 	 * Setup 2nd TLB with same physical address but different virtual
 	 * address with cache enabled. This is done for fast ECC generation.
 	 */
-	program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
+	program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, dram_size, 0);
 
 #ifdef CONFIG_DDR_ECC
 	/*
 	 * If ECC is enabled, initialize the parity bits.
 	 */
-	program_ecc(CFG_DDR_CACHED_ADDR, dram_size);
+	program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, dram_size);
 #endif
 
 	return (dram_size);
diff --git a/board/netstal/hcu5/u-boot.lds b/board/netstal/hcu5/u-boot.lds
index c72e5ba6997..f857ef3c0f3 100644
--- a/board/netstal/hcu5/u-boot.lds
+++ b/board/netstal/hcu5/u-boot.lds
@@ -136,7 +136,7 @@ SECTIONS
    *(COMMON)
   }
 
-  ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+  ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
 
   _end = . ;
   PROVIDE (end = .);