summaryrefslogtreecommitdiff
path: root/board/netstal
diff options
context:
space:
mode:
authorStefan Roese <sr@denx.de>2009-09-24 13:59:57 +0200
committerStefan Roese <sr@denx.de>2009-09-28 10:45:54 +0200
commit95b602bab5fec2fffab07a01ea3947c70d1bacc1 (patch)
treeacee523787d213090cc592029f1d566473bc1fd7 /board/netstal
parent952e7760bfc5b0e3b142b9ce34e7fbb7d008c900 (diff)
ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case
The latest PPC4xx register cleanup patch missed some SDRAM defines. This patch now changes lower case UIC defines to upper case. Also some names are changed to match the naming in the IBM/AMCC users manuals (e.g. mem_mcopt1 -> SDRAM0_CFG). Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/netstal')
-rw-r--r--board/netstal/common/fixed_sdram.c40
1 files changed, 20 insertions, 20 deletions
diff --git a/board/netstal/common/fixed_sdram.c b/board/netstal/common/fixed_sdram.c
index f7baed6e910..2f21fbb4e38 100644
--- a/board/netstal/common/fixed_sdram.c
+++ b/board/netstal/common/fixed_sdram.c
@@ -29,17 +29,17 @@ void show_sdram_registers(void)
u32 value;
printf("SDRAM Controller Registers --\n");
- mfsdram(mem_mcopt1, value);
+ mfsdram(SDRAM0_CFG, value);
printf(" SDRAM0_CFG : 0x%08x\n", value);
- mfsdram(mem_status, value);
+ mfsdram(SDRAM0_STATUS, value);
printf(" SDRAM0_STATUS: 0x%08x\n", value);
- mfsdram(mem_mb0cf, value);
+ mfsdram(SDRAM0_B0CR, value);
printf(" SDRAM0_B0CR : 0x%08x\n", value);
- mfsdram(mem_mb1cf, value);
+ mfsdram(SDRAM0_B1CR, value);
printf(" SDRAM0_B1CR : 0x%08x\n", value);
- mfsdram(mem_sdtr1, value);
+ mfsdram(SDRAM0_TR, value);
printf(" SDRAM0_TR : 0x%08x\n", value);
- mfsdram(mem_rtr, value);
+ mfsdram(SDRAM0_RTR, value);
printf(" SDRAM0_RTR : 0x%08x\n", value);
}
#endif
@@ -50,53 +50,53 @@ long int init_ppc405_sdram(unsigned int dram_size)
printf(__FUNCTION__);
#endif
/* disable memory controller */
- mtsdram(mem_mcopt1, 0x00000000);
+ mtsdram(SDRAM0_CFG, 0x00000000);
udelay (500);
/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
- mtsdram(mem_besra, 0xffffffff);
+ mtsdram(SDRAM0_BESR0, 0xffffffff);
/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
- mtsdram(mem_besrb, 0xffffffff);
+ mtsdram(SDRAM0_BESR1, 0xffffffff);
/* Clear SDRAM0_ECCCFG (disable ECC) */
- mtsdram(mem_ecccf, 0x00000000);
+ mtsdram(SDRAM0_ECCCFG, 0x00000000);
/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
- mtsdram(mem_eccerr, 0xffffffff);
+ mtsdram(SDRAM0_ECCESR, 0xffffffff);
/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2
*/
- mtsdram(mem_sdtr1, 0x008a4015);
+ mtsdram(SDRAM0_TR, 0x008a4015);
/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1
* and refresh timer
*/
switch (dram_size >> 20) {
case 32:
- mtsdram(mem_mb0cf, 0x00062001);
- mtsdram(mem_rtr, 0x07F00000);
+ mtsdram(SDRAM0_B0CR, 0x00062001);
+ mtsdram(SDRAM0_RTR, 0x07F00000);
break;
case 64:
- mtsdram(mem_mb0cf, 0x00084001);
- mtsdram(mem_rtr, 0x04100000);
+ mtsdram(SDRAM0_B0CR, 0x00084001);
+ mtsdram(SDRAM0_RTR, 0x04100000);
break;
case 128:
- mtsdram(mem_mb0cf, 0x000A4001);
- mtsdram(mem_rtr, 0x04100000);
+ mtsdram(SDRAM0_B0CR, 0x000A4001);
+ mtsdram(SDRAM0_RTR, 0x04100000);
break;
default:
printf("Invalid memory size of %d MB given\n", dram_size >> 20);
}
/* Power management idle timer set to the default. */
- mtsdram(mem_pmit, 0x07c00000);
+ mtsdram(SDRAM0_PMIT, 0x07c00000);
udelay (500);
/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */
- mtsdram(mem_mcopt1, 0x90800000);
+ mtsdram(SDRAM0_CFG, 0x90800000);
#ifdef DEBUG
printf("%s: done\n", __FUNCTION__);