diff options
| author | Che-Liang Chiou <clchiou@chromium.org> | 2011-07-05 22:36:34 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2011-08-29 10:58:45 -0700 |
| commit | a092cc78c20fcd1f9ee298f3ead4fa0f9f1e09e3 (patch) | |
| tree | 193fe1f30d4fa8dfab61c2c1f5d401baba393314 /board/nvidia/seaboard | |
| parent | 61199c312d28e85cc8f0ef37d1c0692c484e8bb9 (diff) | |
CHROMIUM: fdt: add gpio polarity to fdt and crossystem data
The raw gpio readings are not the logical values of true/false. A gpio
may connect to device that is either high active or low active. That is,
a raw reading of 1 from low active device actually means "false". In
this context, we refer to this as a gpio's polarity. Note that a gpio
polarity may differ board by board, depending on the actual wiring of
the board.
The u-boot and the crossystem (a user space program) needs the
polarities to correctly interpret the raw gpio readings. The crossystem
needs polarities for the gpio values in the crossystem data blob that
u-boot passes to kernel (these values are "post-interpretation").
Instead, the crossystem is required to read "current" raw gpio readings
and interpret these readings to a user.
Note: I merely copied polarity configuration to kaen and aebl, but I did
not test its correctness.
BUG=chromium-os:16508
TEST=boot on Seaboard
1. Turn on Seaboard with dev switch on and rec switch off
2. Check debug output of u-boot
----------------------------------------
cros_onestop_firmware: polarity:
cros_onestop_firmware: - wpsw: 1
cros_onestop_firmware: - recsw: 0
cros_onestop_firmware: - devsw: 1
cros_onestop_firmware: gpio value:
cros_onestop_firmware: - wpsw: 1
cros_onestop_firmware: - recsw: 0
cros_onestop_firmware: - devsw: 1
----------------------------------------
2. Check /proc/device-tree/crossystem/
----------------------------------------
$ od -x polarity_write_protect_sw
0000000 0000 0100
0000004
$ od -x polarity_recovery_sw
0000000 0000 0000
0000004
$ od -x polarity_developer_sw
0000000 0000 0100
0000004
----------------------------------------
Change-Id: Ie92c31ce0abddf0271e73669b429621deaed76dd
Reviewed-on: http://gerrit.chromium.org/gerrit/3650
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Che-Liang Chiou <clchiou@chromium.org>
Diffstat (limited to 'board/nvidia/seaboard')
| -rw-r--r-- | board/nvidia/seaboard/tegra2-aebl.dts | 5 | ||||
| -rw-r--r-- | board/nvidia/seaboard/tegra2-kaen.dts | 5 | ||||
| -rw-r--r-- | board/nvidia/seaboard/tegra2-seaboard.dts | 5 |
3 files changed, 15 insertions, 0 deletions
diff --git a/board/nvidia/seaboard/tegra2-aebl.dts b/board/nvidia/seaboard/tegra2-aebl.dts index 1dc0e9b2970..46f8b03dc01 100644 --- a/board/nvidia/seaboard/tegra2-aebl.dts +++ b/board/nvidia/seaboard/tegra2-aebl.dts @@ -12,6 +12,11 @@ odmdata = <0x300d8011>; hwid = "ARM AEBL TEST 5789"; machine-arch-id = <3287>; + + /* GPIO polarity: 0=active_low, 1=active_high */ + polarity_write_protect_switch = <1>; + polarity_recovery_switch = <0>; + polarity_developer_switch = <1>; }; aliases { diff --git a/board/nvidia/seaboard/tegra2-kaen.dts b/board/nvidia/seaboard/tegra2-kaen.dts index 00ef5044757..e9761c2e522 100644 --- a/board/nvidia/seaboard/tegra2-kaen.dts +++ b/board/nvidia/seaboard/tegra2-kaen.dts @@ -12,6 +12,11 @@ odmdata = <0x300d8011>; hwid = "ARM KAEN TEST 3084"; machine-arch-id = <3217>; + + /* GPIO polarity: 0=active_low, 1=active_high */ + polarity_write_protect_switch = <1>; + polarity_recovery_switch = <0>; + polarity_developer_switch = <1>; }; aliases { diff --git a/board/nvidia/seaboard/tegra2-seaboard.dts b/board/nvidia/seaboard/tegra2-seaboard.dts index 3d2a3ca62e0..502391de9e9 100644 --- a/board/nvidia/seaboard/tegra2-seaboard.dts +++ b/board/nvidia/seaboard/tegra2-seaboard.dts @@ -12,6 +12,11 @@ odmdata = <0x300d8011>; hwid = "ARM SEABOARD TEST 1176"; machine-arch-id = <3005>; + + /* GPIO polarity: 0=active_low, 1=active_high */ + polarity_write_protect_switch = <1>; + polarity_recovery_switch = <0>; + polarity_developer_switch = <1>; }; aliases { |