diff options
| author | Che-Liang Chiou <clchiou@chromium.org> | 2011-07-06 16:35:57 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2011-08-29 10:58:46 -0700 |
| commit | ec59c46b548ca1fb72ed0aaa5b9913b2e447fe70 (patch) | |
| tree | d2fa05e8c74e8ec009c68bf1e23a323e3e8731bf /board/nvidia/seaboard | |
| parent | 52d0897b475d5110e08dd80f21d6471b428151ee (diff) | |
CHROMIUIM: add gpio port number to crossystem data
BUG=none
TEST=boot and see gpio port number are set properly
Change-Id: Ib4dbd54d7a50b6e31fb90c2c1977babab5f7b78b
Reviewed-on: http://gerrit.chromium.org/gerrit/3670
Tested-by: Che-Liang Chiou <clchiou@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Diffstat (limited to 'board/nvidia/seaboard')
| -rw-r--r-- | board/nvidia/seaboard/tegra2-aebl.dts | 5 | ||||
| -rw-r--r-- | board/nvidia/seaboard/tegra2-kaen.dts | 5 | ||||
| -rw-r--r-- | board/nvidia/seaboard/tegra2-seaboard.dts | 5 |
3 files changed, 15 insertions, 0 deletions
diff --git a/board/nvidia/seaboard/tegra2-aebl.dts b/board/nvidia/seaboard/tegra2-aebl.dts index c4a83a28955..e85c8afe824 100644 --- a/board/nvidia/seaboard/tegra2-aebl.dts +++ b/board/nvidia/seaboard/tegra2-aebl.dts @@ -14,6 +14,11 @@ hwid = "ARM AEBL TEST 5789"; machine-arch-id = <3287>; + /* Chrome OS specific GPIO port number */ + gpio_port_write_protect_switch = <59>; + gpio_port_recovery_switch = <56>; + gpio_port_developer_switch = <168>; + /* GPIO polarity: 0=active_low, 1=active_high */ polarity_write_protect_switch = <1>; polarity_recovery_switch = <0>; diff --git a/board/nvidia/seaboard/tegra2-kaen.dts b/board/nvidia/seaboard/tegra2-kaen.dts index c74e69ac09f..64738ebe1aa 100644 --- a/board/nvidia/seaboard/tegra2-kaen.dts +++ b/board/nvidia/seaboard/tegra2-kaen.dts @@ -14,6 +14,11 @@ hwid = "ARM KAEN TEST 3084"; machine-arch-id = <3217>; + /* Chrome OS specific GPIO port number */ + gpio_port_write_protect_switch = <59>; + gpio_port_recovery_switch = <56>; + gpio_port_developer_switch = <168>; + /* GPIO polarity: 0=active_low, 1=active_high */ polarity_write_protect_switch = <1>; polarity_recovery_switch = <0>; diff --git a/board/nvidia/seaboard/tegra2-seaboard.dts b/board/nvidia/seaboard/tegra2-seaboard.dts index c9ef1450e02..0261e0da5a7 100644 --- a/board/nvidia/seaboard/tegra2-seaboard.dts +++ b/board/nvidia/seaboard/tegra2-seaboard.dts @@ -14,6 +14,11 @@ hwid = "ARM SEABOARD TEST 1176"; machine-arch-id = <3005>; + /* Chrome OS specific GPIO port number */ + gpio_port_write_protect_switch = <59>; + gpio_port_recovery_switch = <56>; + gpio_port_developer_switch = <168>; + /* GPIO polarity: 0=active_low, 1=active_high */ polarity_write_protect_switch = <1>; polarity_recovery_switch = <0>; |