diff options
author | Teresa Remmet <t.remmet@phytec.de> | 2024-05-28 15:35:14 +0200 |
---|---|---|
committer | Fabio Estevam <festevam@gmail.com> | 2024-06-03 12:14:00 -0300 |
commit | 8869c2324d6ba982a607f0ed367396a9b51b896c (patch) | |
tree | 05bafef49228efe66fe2178ba4c2cb245b988676 /board/phytec/phycore_imx8mp/spl.c | |
parent | cff451e03ff3c9612723c8ab2b8b5be525538936 (diff) |
board: phytec: phycore_imx8mp: Make RAM size configuration fix
We might not be able to always rely on the EEPROM introspection data.
So add a config option alternative which configures the RAM size
to a fix value.
We still try to read the EEPROM introspection data at this point.
So we can print the SoM information if available.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Diffstat (limited to 'board/phytec/phycore_imx8mp/spl.c')
-rw-r--r-- | board/phytec/phycore_imx8mp/spl.c | 34 |
1 files changed, 26 insertions, 8 deletions
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 855aa1a9009..7fdb96f1c14 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -49,20 +49,38 @@ void spl_dram_init(void) ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR, EEPROM_ADDR_FALLBACK); - if (ret) + if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX)) goto out; ret = phytec_imx8m_detect(NULL); if (!ret) phytec_print_som_info(NULL); - u8 rev = phytec_get_rev(NULL); - u8 somtype = phytec_get_som_type(NULL); - - if (rev != PHYTEC_EEPROM_INVAL && (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) - use_2ghz_timings = true; - - size = phytec_get_imx8m_ddr_size(NULL); + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_1GB)) + size = PHYTEC_IMX8MP_DDR_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_2GB)) + size = PHYTEC_IMX8MP_DDR_2GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_4GB)) + size = PHYTEC_IMX8MP_DDR_4GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_8GB)) + size = PHYTEC_IMX8MP_DDR_8GB; + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS)) { + if (size == PHYTEC_IMX8MP_DDR_4GB) + size = PHYTEC_IMX8MP_DDR_4GB_2GHZ; + else + use_2ghz_timings = true; + } + } else { + u8 rev = phytec_get_rev(NULL); + u8 somtype = phytec_get_som_type(NULL); + + if (rev != PHYTEC_EEPROM_INVAL && + (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1))) + use_2ghz_timings = true; + + size = phytec_get_imx8m_ddr_size(NULL); + } switch (size) { case PHYTEC_IMX8MP_DDR_1GB: |