diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2010-12-23 15:40:12 -0500 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-01-09 18:06:50 +0100 |
| commit | 8ef583a0351590a91394499eb5ca2ab8a703d959 (patch) | |
| tree | 36dafbd4bdd7e46130aec04bbc0dbfe26e896d9f /board/prodrive | |
| parent | 4ffeab2cc00b61bc4616d9e3c25d33937b0feb34 (diff) | |
miiphy: convert to linux/mii.h
The include/miiphy.h header duplicates a lot of things from linux/mii.h.
So punt all the things that overlap to keep the API simple and to make
merging between U-Boot and Linux simpler.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'board/prodrive')
| -rw-r--r-- | board/prodrive/p3mx/mv_eth.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/board/prodrive/p3mx/mv_eth.c b/board/prodrive/p3mx/mv_eth.c index 567ae99d06d..fac7633b77a 100644 --- a/board/prodrive/p3mx/mv_eth.c +++ b/board/prodrive/p3mx/mv_eth.c @@ -586,16 +586,16 @@ static int mv64460_eth_real_open (struct eth_device *dev) } #endif /* defined(CONFIG_PHY_RESET) */ - miiphy_read (dev->name, reg, PHY_BMSR, ®_short); + miiphy_read (dev->name, reg, MII_BMSR, ®_short); /* * Wait if PHY is capable of autonegotiation and autonegotiation is not complete */ - if ((reg_short & PHY_BMSR_AUTN_ABLE) - && !(reg_short & PHY_BMSR_AUTN_COMP)) { + if ((reg_short & BMSR_ANEGCAPABLE) + && !(reg_short & BMSR_ANEGCOMPLETE)) { puts ("Waiting for PHY auto negotiation to complete"); i = 0; - while (!(reg_short & PHY_BMSR_AUTN_COMP)) { + while (!(reg_short & BMSR_ANEGCOMPLETE)) { /* * Timeout reached ? */ @@ -608,7 +608,7 @@ static int mv64460_eth_real_open (struct eth_device *dev) putc ('.'); } udelay (1000); /* 1 ms */ - miiphy_read (dev->name, reg, PHY_BMSR, ®_short); + miiphy_read (dev->name, reg, MII_BMSR, ®_short); } puts (" done\n"); @@ -2241,20 +2241,20 @@ int phy_setup_aneg (char *devname, unsigned char addr) unsigned short ctl, adv; /* Setup standard advertise */ - miiphy_read (devname, addr, PHY_ANAR, &adv); - adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 | - PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | - PHY_ANLPAR_10); - miiphy_write (devname, addr, PHY_ANAR, adv); + miiphy_read (devname, addr, MII_ADVERTISE, &adv); + adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 | + LPA_100FULL | LPA_100HALF | LPA_10FULL | + LPA_10HALF); + miiphy_write (devname, addr, MII_ADVERTISE, adv); - miiphy_read (devname, addr, PHY_1000BTCR, &adv); + miiphy_read (devname, addr, MII_CTRL1000, &adv); adv |= (0x0300); - miiphy_write (devname, addr, PHY_1000BTCR, adv); + miiphy_write (devname, addr, MII_CTRL1000, adv); /* Start/Restart aneg */ - miiphy_read (devname, addr, PHY_BMCR, &ctl); - ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - miiphy_write (devname, addr, PHY_BMCR, ctl); + miiphy_read (devname, addr, MII_BMCR, &ctl); + ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); + miiphy_write (devname, addr, MII_BMCR, ctl); return 0; } |