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authorVladimir Barinov <vladimir.barinov@cogentembedded.com>2015-02-24 18:55:46 +0200
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>2015-02-25 14:20:10 +0900
commit275ec28eed3d09bd924457b02ce29203172ae808 (patch)
treef10698ba01ba7cb3c1982aa21c323e3c7e77c4d1 /board/renesas
parent80069b7e4d9d1e77f1c3d9ba5a1f117990096d1d (diff)
arm: rmobile: silk: Add support SDHI
This adds GPIO configuration and initialization function of SDHI on Silk board Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'board/renesas')
-rw-r--r--board/renesas/silk/silk.c35
1 files changed, 34 insertions, 1 deletions
diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c
index 1838c4ba4a..021baabc65 100644
--- a/board/renesas/silk/silk.c
+++ b/board/renesas/silk/silk.c
@@ -20,6 +20,7 @@
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/mmc.h>
+#include <asm/arch/sh_sdhi.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
@@ -47,6 +48,10 @@ void s_init(void)
#define ETHER_MSTP813 (1 << 13)
#define IIC1_MSTP323 (1 << 23)
#define MMC0_MSTP315 (1 << 15)
+#define SDHI1_MSTP312 (1 << 12)
+
+#define SD1CKCR 0xE6150078
+#define SD1_97500KHZ 0x7
int board_early_init_f(void)
{
@@ -66,6 +71,16 @@ int board_early_init_f(void)
/* MMC */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
#endif
+
+#ifdef CONFIG_SH_SDHI
+ /* SDHI1 */
+ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI1_MSTP312);
+
+ /*
+ * Set SD1 to the 97.5MHz
+ */
+ writel(SD1_97500KHZ, SD1CKCR);
+#endif
return 0;
}
@@ -139,7 +154,7 @@ int board_eth_init(bd_t *bis)
int board_mmc_init(bd_t *bis)
{
- int ret = 0;
+ int ret = -ENODEV;
#ifdef CONFIG_SH_MMCIF
/* MMC0 */
@@ -148,6 +163,24 @@ int board_mmc_init(bd_t *bis)
ret = mmcif_mmc_init();
#endif
+
+#ifdef CONFIG_SH_SDHI
+ gpio_request(GPIO_FN_SD1_DATA0, NULL);
+ gpio_request(GPIO_FN_SD1_DATA1, NULL);
+ gpio_request(GPIO_FN_SD1_DATA2, NULL);
+ gpio_request(GPIO_FN_SD1_DATA3, NULL);
+ gpio_request(GPIO_FN_SD1_CLK, NULL);
+ gpio_request(GPIO_FN_SD1_CMD, NULL);
+ gpio_request(GPIO_FN_SD1_CD, NULL);
+
+ /* SDHI 1 */
+ gpio_request(GPIO_GP_4_26, NULL);
+ gpio_request(GPIO_GP_4_29, NULL);
+ gpio_direction_output(GPIO_GP_4_26, 1);
+ gpio_direction_output(GPIO_GP_4_29, 1);
+
+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
+#endif
return ret;
}