Merge branch 'master' of git://git.denx.de/u-boot-arm

4 files changed, 0 insertions, 559 deletions

diff --git a/board/ti/omap1510inn/Makefile b/board/ti/omap1510inn/Makefile
deleted file mode 100644
index ad5a7eb94e9..00000000000
--- a/board/ti/omap1510inn/Makefile
+++ /dev/null
@@ -1,29 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= omap1510innovator.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/ti/omap1510inn/config.mk b/board/ti/omap1510inn/config.mk
deleted file mode 100644
index 67fe0bdf8fe..00000000000
--- a/board/ti/omap1510inn/config.mk
+++ /dev/null
@@ -1,25 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2003
-# Texas Instruments, <www.ti.com>
-# Kshitij Gupta <Kshitij@ti.com>
-#
-# TI Innovator board with OMAP1510 (ARM925T) cpu
-# see http://www.ti.com/ for more information on Texas Insturments
-#
-# Innovator has 1 bank of 256 MB SDRAM
-# Physical Address:
-# 1000'0000 to 2000'0000
-#
-#
-# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000  (mem base + reserved)
-#
-# we load ourself to 1108'0000
-#
-#
-
-
-CONFIG_SYS_TEXT_BASE = 0x11080000
diff --git a/board/ti/omap1510inn/lowlevel_init.S b/board/ti/omap1510inn/lowlevel_init.S
deleted file mode 100644
index 4d3ec39a659..00000000000
--- a/board/ti/omap1510inn/lowlevel_init.S
+++ /dev/null
@@ -1,380 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- *
- * -- Some bits of code used from rrload's head_OMAP1510.s --
- * Copyright (C) 2002 RidgeRun, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-
-#if defined(CONFIG_OMAP1510)
-#include <./configs/omap1510.h>
-#endif
-
-#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
-
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE        /* sdram load addr from config.mk */
-
-.globl lowlevel_init
-lowlevel_init:
-
-	/*
-	 * Configure 1510 pins functions to match our board.
-	 */
-	ldr     r0, REG_PULL_DWN_CTRL_0
-	ldr     r1, VAL_PULL_DWN_CTRL_0
-	str     r1, [r0]
-	ldr     r0, REG_PULL_DWN_CTRL_1
-	ldr     r1, VAL_PULL_DWN_CTRL_1
-	str     r1, [r0]
-	ldr     r0, REG_PULL_DWN_CTRL_2
-	ldr     r1, VAL_PULL_DWN_CTRL_2
-	str     r1, [r0]
-	ldr     r0, REG_PULL_DWN_CTRL_3
-	ldr     r1, VAL_PULL_DWN_CTRL_3
-	str     r1, [r0]
-	ldr     r0, REG_FUNC_MUX_CTRL_4
-	ldr     r1, VAL_FUNC_MUX_CTRL_4
-	str     r1, [r0]
-	ldr     r0, REG_FUNC_MUX_CTRL_5
-	ldr     r1, VAL_FUNC_MUX_CTRL_5
-	str     r1, [r0]
-	ldr     r0, REG_FUNC_MUX_CTRL_6
-	ldr     r1, VAL_FUNC_MUX_CTRL_6
-	str     r1, [r0]
-	ldr     r0, REG_FUNC_MUX_CTRL_7
-	ldr     r1, VAL_FUNC_MUX_CTRL_7
-	str     r1, [r0]
-	ldr     r0, REG_FUNC_MUX_CTRL_8
-	ldr     r1, VAL_FUNC_MUX_CTRL_8
-	str     r1, [r0]
-	ldr     r0, REG_FUNC_MUX_CTRL_9
-	ldr     r1, VAL_FUNC_MUX_CTRL_9
-	str     r1, [r0]
-	ldr     r0, REG_FUNC_MUX_CTRL_A
-	ldr     r1, VAL_FUNC_MUX_CTRL_A
-	str     r1, [r0]
-	ldr     r0, REG_FUNC_MUX_CTRL_B
-	ldr     r1, VAL_FUNC_MUX_CTRL_B
-	str     r1, [r0]
-	ldr     r0, REG_FUNC_MUX_CTRL_C
-	ldr     r1, VAL_FUNC_MUX_CTRL_C
-	str     r1, [r0]
-	ldr     r0, REG_FUNC_MUX_CTRL_D
-	ldr     r1, VAL_FUNC_MUX_CTRL_D
-	str     r1, [r0]
-	ldr     r0, REG_VOLTAGE_CTRL_0
-	ldr     r1, VAL_VOLTAGE_CTRL_0
-	str     r1, [r0]
-	ldr     r0, REG_TEST_DBG_CTRL_0
-	ldr     r1, VAL_TEST_DBG_CTRL_0
-	str     r1, [r0]
-	ldr     r0, REG_MOD_CONF_CTRL_0
-	ldr     r1, VAL_MOD_CONF_CTRL_0
-	str     r1, [r0]
-
-	/* Move to 1510 mode */
-	ldr     r0, REG_COMP_MODE_CTRL_0
-	ldr     r1, VAL_COMP_MODE_CTRL_0
-	str     r1, [r0]
-
-	/* Set up Traffic Ctlr*/
-	ldr r0, REG_TC_IMIF_PRIO
-	mov r1, #0x0
-	str r1, [r0]
-	ldr r0, REG_TC_EMIFS_PRIO
-	str r1, [r0]
-	ldr r0, REG_TC_EMIFF_PRIO
-	str r1, [r0]
-
-	ldr r0, REG_TC_EMIFS_CONFIG
-	ldr r1, [r0]
-	bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
-	bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
-	str r1, [r0]        /* EMIFS GlB Configuration. (value 0x12 most likely) */
-
-	/* Setup some clock domains */
-	ldr r1, =OMAP1510_CLKS
-	ldr r0, REG_ARM_IDLECT2
-	strh r1, [r0]  /* CLKM, Clock domain control. */
-
-	mov r1, #0x01  /* PER_EN bit */
-	ldr r0, REG_ARM_RSTCT2
-	strh r1, [r0]  /* CLKM; Peripheral reset. */
-
-	/* Set CLKM to Sync-Scalable  */
-	/* I supposidly need to enable the dsp clock before switching */
-	mov r1, #0x1000
-	ldr r0, REG_ARM_SYSST
-	strh r1, [r0]
-	mov r0, #0x400
-1:
-	subs r0, r0, #0x1   /* wait for any bubbles to finish */
-	bne 1b
-
-	ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
-	ldr r0, REG_ARM_CKCTL
-	strh r1, [r0]
-
-	/* setup DPLL 1 */
-	ldr r1, VAL_DPLL1_CTL
-	ldr r0, REG_DPLL1_CTL
-	strh r1, [r0]
-	ands r1, r1, #0x10  /* Check if PLL is enabled. */
-	beq lock_end        /* Do not look for lock if BYPASS selected */
-2:
-	ldrh r1, [r0]
-	ands r1, r1, #0x01  /* Check the LOCK bit. */
-	beq 2b              /* ...loop until bit goes hi. */
-lock_end:
-
-	/* Set memory timings corresponding to the new clock speed */
-
-	/* Check execution location to determine current execution location
-	 * and branch to appropriate initialization code.
-	 */
-	mov r0, #0x10000000                 /* Load physical SDRAM base. */
-	mov r1, pc                          /* Get current execution location. */
-	/* Zero all but top 6 bits of PC, as they alone detect whether an
-	 * address is in the range 0x1000:0000-0x13ff:ffff, the 64M sized
-	 * valid range for SDRAM on the OMAP 1510/5910.
-	 */
-	and r1, r1, #0xfc000000
-	cmp r1, r0			/* Compare. */
-	beq skip_sdram			/* Skip over EMIF-fast initialization
-					 * if running from SDRAM.
-					 */
-
-	/*
-	 * Delay for SDRAM initialization.
-	 */
-	mov r3, #0x1800                        /* value should be checked */
-3:
-	subs r3, r3, #0x1                     /* Decrement count */
-	bne 3b
-
-	/*
-	 * Set SDRAM control values. Disable refresh before MRS command.
-	 */
-	ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
-	bic r3, r0, #0xC                    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
-	orr r3, r3, #0x8000000              /* (BIT27) Disable CLK when Power down or Self-Refresh */
-	orr r3, r3, #0x4000000              /* BIT26 Power Down Enable */
-	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
-	str r3, [r2]                        /* Store the passed value with AR disabled. */
-
-	ldr r1, VAL_TC_EMIFF_MRS            /* get MRS value */
-	ldr r2, REG_TC_EMIFF_MRS            /* Point to MRS register. */
-	str r1, [r2]                        /* Store the passed value.*/
-
-	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
-	str r0, [r2]                        /* Store the passed value. */
-
-	/*
-	 * Delay for SDRAM initialization.
-	 */
-	mov r3, #0x1800
-4:
-	subs r3, r3, #1                     /* Decrement count. */
-	bne 4b
-
-skip_sdram:
-
-	/* slow interface */
-	ldr r1, VAL_TC_EMIFS_CS0_CONFIG
-	ldr r0, REG_TC_EMIFS_CS0_CONFIG
-	str r1, [r0] /* Chip Select 0 */
-	ldr r1, VAL_TC_EMIFS_CS1_CONFIG
-	ldr r0, REG_TC_EMIFS_CS1_CONFIG
-	str r1, [r0] /* Chip Select 1 */
-	ldr r1, VAL_TC_EMIFS_CS2_CONFIG
-	ldr r0, REG_TC_EMIFS_CS2_CONFIG
-	str r1, [r0] /* Chip Select 2 */
-	ldr r1, VAL_TC_EMIFS_CS3_CONFIG
-	ldr r0, REG_TC_EMIFS_CS3_CONFIG
-	str r1, [r0] /* Chip Select 3 */
-
- /* Next, Enable the RS232 Line Drivers in the FPGA. */
- /* Also, power on the audio CODEC's amplifier here, */
- /* which will make a noise on the audio output. */
- /* This is done here instead of in the kernel so there */
- /* isn't a loud popping noise at the start of each */
- /* song. */
- /* Also, disable the CODEC's clocks. */
- /* omap1510-HelenP1 [specific] */
-
-	ldr r0, REG_FPGA_POWER
-	mov r1, #0
-	ldr r2, REG_FPGA_DIP_SWITCH
-	ldrb r3, [r2]
-	cmp r3, #0x8
-	movne r1, #0x62     /* Enable the RS232 Line Drivers in the EPLD */
-	strb r1, [r0]
-	ldr r0, REG_FPGA_AUDIO
-	mov r1, #0x0     /* Disable sound driver (CODEC clocks) */
-	strb r1, [r0]
-
-	/* back to arch calling code */
-	mov	pc, lr
-
-/* the literal pools origin */
-	.ltorg
-
-/* OMAP configuration registers */
-REG_FUNC_MUX_CTRL_0:		/* 32 bits */
-	.word 0xfffe1000
-REG_FUNC_MUX_CTRL_1:		/* 32 bits */
-	.word 0xfffe1004
-REG_FUNC_MUX_CTRL_2:		/* 32 bits */
-	.word 0xfffe1008
-REG_COMP_MODE_CTRL_0:		/* 32 bits */
-	.word 0xfffe100c
-REG_FUNC_MUX_CTRL_3:		/* 32 bits */
-	.word 0xfffe1010
-REG_FUNC_MUX_CTRL_4:		/* 32 bits */
-	.word 0xfffe1014
-REG_FUNC_MUX_CTRL_5:		/* 32 bits */
-	.word 0xfffe1018
-REG_FUNC_MUX_CTRL_6:		/* 32 bits */
-	.word 0xfffe101c
-REG_FUNC_MUX_CTRL_7:		/* 32 bits */
-	.word 0xfffe1020
-REG_FUNC_MUX_CTRL_8:		/* 32 bits */
-	.word 0xfffe1024
-REG_FUNC_MUX_CTRL_9:		/* 32 bits */
-	.word 0xfffe1028
-REG_FUNC_MUX_CTRL_A:		/* 32 bits */
-	.word 0xfffe102C
-REG_FUNC_MUX_CTRL_B:		/* 32 bits */
-	.word 0xfffe1030
-REG_FUNC_MUX_CTRL_C:		/* 32 bits */
-	.word 0xfffe1034
-REG_FUNC_MUX_CTRL_D:		/* 32 bits */
-	.word 0xfffe1038
-REG_PULL_DWN_CTRL_0:		/* 32 bits */
-	.word 0xfffe1040
-REG_PULL_DWN_CTRL_1:		/* 32 bits */
-	.word 0xfffe1044
-REG_PULL_DWN_CTRL_2:		/* 32 bits */
-	.word 0xfffe1048
-REG_PULL_DWN_CTRL_3:		/* 32 bits */
-	.word 0xfffe104c
-REG_VOLTAGE_CTRL_0:		/* 32 bits */
-	.word 0xfffe1060
-REG_TEST_DBG_CTRL_0:		/* 32 bits */
-	.word 0xfffe1070
-REG_MOD_CONF_CTRL_0:		/* 32 bits */
-	.word 0xfffe1080
-REG_TC_IMIF_PRIO:		/* 32 bits */
-	.word 0xfffecc00
-REG_TC_EMIFS_PRIO:		/* 32 bits */
-	.word 0xfffecc04
-REG_TC_EMIFF_PRIO:		/* 32 bits */
-	.word 0xfffecc08
-REG_TC_EMIFS_CONFIG:		/* 32 bits */
-	.word 0xfffecc0c
-REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
-	.word 0xfffecc10
-REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
-	.word 0xfffecc14
-REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
-	.word 0xfffecc18
-REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
-	.word 0xfffecc1c
-REG_TC_EMIFF_SDRAM_CONFIG:	/* 32 bits */
-	.word 0xfffecc20
-REG_TC_EMIFF_MRS:		/* 32 bits */
-	.word 0xfffecc24
-/* MPU clock/reset/power mode control registers */
-REG_ARM_CKCTL:			/* 16 bits */
-	.word 0xfffece00
-REG_ARM_IDLECT2:		/* 16 bits */
-	.word 0xfffece08
-REG_ARM_RSTCT2:			/* 16 bits */
-	.word 0xfffece14
-REG_ARM_SYSST:			/* 16 bits */
-	.word 0xfffece18
-/* DPLL control registers */
-REG_DPLL1_CTL:			/* 16 bits */
-	.word 0xfffecf00
-/* identification code register */
-REG_IDCODE:			/* 32 bits */
-	.word 0xfffed404
-
-/* Innovator specific */
-REG_FPGA_LED_DIGIT:		/* 8 bits (not used on Innovator) */
-	.word 0x08000003
-REG_FPGA_POWER:			/* 8 bits */
-	.word 0x08000005
-REG_FPGA_AUDIO:			/* 8 bits (not used on Innovator) */
-	.word 0x0800000c
-REG_FPGA_DIP_SWITCH:		/* 8 bits (not used on Innovator) */
-	.word 0x0800000e
-
-VAL_COMP_MODE_CTRL_0:
-	.word 0x0000eaef
-VAL_FUNC_MUX_CTRL_4:
-	.word 0x00000000
-VAL_FUNC_MUX_CTRL_5:
-	.word 0x00000000
-VAL_FUNC_MUX_CTRL_6:
-	.word 0x00000001
-VAL_FUNC_MUX_CTRL_7:
-	.word 0x00000000
-VAL_FUNC_MUX_CTRL_8:
-	.word 0x10001200
-VAL_FUNC_MUX_CTRL_9:
-	.word 0x01201012
-VAL_FUNC_MUX_CTRL_A:
-	.word 0x00000248
-VAL_FUNC_MUX_CTRL_B:
-	.word 0x00000248
-VAL_FUNC_MUX_CTRL_C:
-	.word 0x09000000
-VAL_FUNC_MUX_CTRL_D:
-	.word 0x00000000
-VAL_PULL_DWN_CTRL_0:
-	.word 0x11a10000
-VAL_PULL_DWN_CTRL_1:
-	.word 0x2e047fff
-VAL_PULL_DWN_CTRL_2:
-	.word 0xffd603a6
-VAL_PULL_DWN_CTRL_3:
-	.word 0x00003e03
-VAL_VOLTAGE_CTRL_0:
-	.word 0x00000007
-VAL_TEST_DBG_CTRL_0:
-	/*  See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 .
-	 *   This slows down internal SRAM accesses.
-	 */
-	.word 0x00000007
-VAL_MOD_CONF_CTRL_0:
-	.word 0x0b000008
-VAL_ARM_CKCTL:
-	.word 0x010f
-VAL_DPLL1_CTL:
-	.word 0x2710
-VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
-	.word 0x00001149
-VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
-	.word 0x00004158
-VAL_TC_EMIFS_CS0_CONFIG:
-	.word 0x002130b0
-VAL_TC_EMIFS_CS1_CONFIG:
-	.word 0x0000f559
-VAL_TC_EMIFS_CS2_CONFIG:
-	.word 0x000055f0
-VAL_TC_EMIFS_CS3_CONFIG:
-	.word 0x00003331
-VAL_TC_EMIFF_SDRAM_CONFIG:
-	.word 0x010290fc
-VAL_TC_EMIFF_MRS:
-	.word 0x00000027
diff --git a/board/ti/omap1510inn/omap1510innovator.c b/board/ti/omap1510inn/omap1510innovator.c
deleted file mode 100644
index a2a33a050b8..00000000000
--- a/board/ti/omap1510inn/omap1510innovator.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void flash__init (void);
-static void ether__init (void);
-
-static inline void delay (unsigned long loops)
-{
-	__asm__ volatile ("1:\n"
-			  "subs %0, %1, #1\n"
-			  "bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
-	/* arch number of OMAP 1510-Board */
-	gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x10000100;
-
-/* kk - this speeds up your boot a quite a bit.  However to make it
- *  work, you need make sure your kernel startup flush bug is fixed.
- *  ... rkw ...
- */
-	icache_enable ();
-
-	flash__init ();
-	ether__init ();
-	return 0;
-}
-
-
-int misc_init_r (void)
-{
-	/* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */
-	/* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */
-
-	/* setup gpio direction to match board (no floats!) */
-	/**gdir = 0xCFF9; */
-	/**mdir = 0x103F; */
-
-	return (0);
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-static void flash__init (void)
-{
-#define CS0_CHIP_SELECT_REG 0xfffecc10
-#define CS3_CHIP_SELECT_REG 0xfffecc1c
-#define EMIFS_GlB_Config_REG 0xfffecc0c
-
-	{
-		unsigned int regval;
-
-		regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
-		regval = regval | 0x0001;	/* Turn off write protection for flash devices. */
-		if (regval & 0x0002) {
-			regval = regval & 0xfffd;	/* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */
-			/* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */
-			/* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */
-			/* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */
-		}
-		*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
-	}
-}
-
-
-/******************************
- Routine:
- Description:
-******************************/
-static void ether__init (void)
-{
-#define ETH_CONTROL_REG 0x0800000b
-	/* take the Ethernet controller out of reset and wait
-	 * for the EEPROM load to complete.
-	 */
-	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
-	udelay (3);
-}
-
-
-int dram_init (void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_LAN91C96
-	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-#endif
-	return rc;
-}
-#endif