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authorWolfgang Denk <wd@denx.de>2010-10-27 22:48:30 +0200
committerWolfgang Denk <wd@denx.de>2010-10-27 22:48:30 +0200
commit071bc923308832bbc541a887fece767d79a6dc7a (patch)
tree8cadd6c50f93c6e3e7c406813bb94f30e4c0b080 /board/xes
parent57ff9f2421244db4f27649d1e13393d2b85f224d (diff)
Coding Style cleanup
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'board/xes')
-rw-r--r--board/xes/common/fsl_8xxx_misc.c10
-rw-r--r--board/xes/xpedite550x/ddr.c21
2 files changed, 14 insertions, 17 deletions
diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c
index b7fa6950b07..36e9146654c 100644
--- a/board/xes/common/fsl_8xxx_misc.c
+++ b/board/xes/common/fsl_8xxx_misc.c
@@ -52,11 +52,9 @@ uint get_board_derivative(void)
#endif
/*
- * The top 4 lines of the local bus address are pulled low/high and
- * can be read to determine the least significant digit of a board's
- * model number.
- */
+ * The top 4 lines of the local bus address are pulled low/high and
+ * can be read to determine the least significant digit of a board's
+ * model number.
+ */
return gur->gpporcr >> 28;
}
-
-
diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c
index 718cd989bbf..38a459715fd 100644
--- a/board/xes/xpedite550x/ddr.c
+++ b/board/xes/xpedite550x/ddr.c
@@ -55,16 +55,16 @@ unsigned int fsl_ddr_get_mem_data_rate(void)
* There are traditionally three board-specific SDRAM timing parameters
* which must be calculated based on the particular PCB artwork. These are:
* 1.) CPO (Read Capture Delay)
- * - TIMING_CFG_2 register
- * Source: Calculation based on board trace lengths and
- * chip-specific internal delays.
+ * - TIMING_CFG_2 register
+ * Source: Calculation based on board trace lengths and
+ * chip-specific internal delays.
* 2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
- * - DDR_SDRAM_CLK_CNTL register
- * Source: Signal Integrity Simulations
+ * - DDR_SDRAM_CLK_CNTL register
+ * Source: Signal Integrity Simulations
* 3.) 2T Timing on Addr/Ctl
- * - TIMING_CFG_2 register
- * Source: Signal Integrity Simulations
- * Usually only needed with heavy load/very high speed (>DDR2-800)
+ * - TIMING_CFG_2 register
+ * Source: Signal Integrity Simulations
+ * Usually only needed with heavy load/very high speed (>DDR2-800)
*
* ====== XPedite550x DDR3-800 read delay calculations ======
*
@@ -82,14 +82,14 @@ typedef struct {
const board_specific_parameters_t board_specific_parameters[][20] = {
{
/* Controller 0 */
- {
+ {
/* DDR3-600/667 */
.datarate_mhz_low = 500,
.datarate_mhz_high = 750,
.clk_adjust = 5,
.cpo = 31,
},
- {
+ {
/* DDR3-800 */
.datarate_mhz_low = 750,
.datarate_mhz_high = 850,
@@ -162,4 +162,3 @@ void fsl_ddr_board_options(memctl_options_t *popts,
popts->rtt_override = 1;
popts->rtt_override_value = 3;
}
-