ppc4xx: Replace 4xx lowercase SPR references

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>

6 files changed, 10 insertions, 10 deletions

diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index 2ab944ddf0e..f22a1c28888 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -142,7 +142,7 @@ int board_early_init_f(void)
 		reg |= CPR0_ICFG_RLI_MASK;
 		mtcpr(clk_icfg, reg);
 
-		mtspr(dbcr0, 0x20000000); /* do chip reset */
+		mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
 	}
 
 	/*
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index 24caa4686c3..1738f543885 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -688,7 +688,7 @@ int misc_init_r (void)
 	start=get_timer(0);
 	/* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
 	if (mfdcr(strap) & PSR_ROM_LOC)
-	       mtspr(ccr0, (mfspr(ccr0) & ~0x80));
+	       mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
 
 	return (0);
 }
diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
index f31a5e8f87f..677437d09ea 100644
--- a/board/mpl/pip405/pip405.c
+++ b/board/mpl/pip405/pip405.c
@@ -669,7 +669,7 @@ int misc_init_r (void)
 
 	/* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
 	if (mfdcr(strap) & PSR_ROM_LOC)
-	       mtspr(ccr0, (mfspr(ccr0) & ~0x80));
+	       mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
 
 	return (0);
 }
diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
index 6f4ec296cb2..5eb33d37fac 100644
--- a/board/netstal/hcu5/hcu5.c
+++ b/board/netstal/hcu5/hcu5.c
@@ -89,8 +89,8 @@ int board_early_init_f(void)
 		/*
 		 * Initiate system reset in debug control register DBCR
 		 */
-		dbcr = mfspr(dbcr0);
-		mtspr(dbcr0, dbcr | CHIP_RESET);
+		dbcr = mfspr(SPRN_DBCR0);
+		mtspr(SPRN_DBCR0, dbcr | CHIP_RESET);
 	}
 	mtsdr(SDR0_CP440, 0x0EAAEA02);  /* [Nto1] = 1*/
 #endif
@@ -307,14 +307,14 @@ int misc_init_r(void)
 	/* We cannot easily enable trace before, as there are other
 	 * routines messing around with sdr0_pfc1. And I do not need it.
 	 */
-	if (mfspr(dbcr0) & 0x80000000) {
+	if (mfspr(SPRN_DBCR0) & 0x80000000) {
 		/* External debugger alive
 		 * enable trace facilty for Lauterbach
 		 * CCR0[DTB]=0		Enable broadcast of trace information
 		 * SDR0_PFC0[TRE]	Trace signals are enabled instead of
 		 *			GPIO49-63
 		 */
-	        mtspr(ccr0, mfspr(ccr0)  &~ (CCR0_DTB));
+	        mtspr(SPRN_CCR0, mfspr(SPRN_CCR0)  &~ (CCR0_DTB));
 		mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE);
 	}
 	return 0;
diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c
index f59bd7d1895..5c2ec356397 100644
--- a/board/netstal/hcu5/sdram.c
+++ b/board/netstal/hcu5/sdram.c
@@ -144,7 +144,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes)
 	u32 *magicPtr;
 	u32 magic;
 
-	if ((mfspr(dbcr0) & 0x80000000) == 0) {
+	if ((mfspr(SPRN_DBCR0) & 0x80000000) == 0) {
 		/* only if no external debugger is alive!
 		 * Check whether vxWorks is using EDR logging, if yes zero
 		 * also PostMortem and user reserved memory
@@ -182,7 +182,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes)
 	 * If not done, then we could get an interrupt later on when
 	 * exceptions are enabled.
 	 */
-	mtspr(mcsr, mfspr(mcsr));
+	mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
 
 	/* Set 'int_mask' parameter to functionnal value */
 	mfsdram(DDR0_01, val);
diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c
index 66ed95fb9dd..67c1b0bbeac 100644
--- a/board/netstal/mcu25/mcu25.c
+++ b/board/netstal/mcu25/mcu25.c
@@ -77,7 +77,7 @@ int board_early_init_f (void)
 	out32(GPIO0_OR,		CONFIG_SYS_GPIO0_OR );
 	out32(GPIO0_TCR,	CONFIG_SYS_GPIO0_TCR);
 	out32(GPIO0_ODR,	CONFIG_SYS_GPIO0_ODR);
-	mtspr(ccr0,      0x00700000);
+	mtspr(SPRN_CCR0,      0x00700000);
 
 	return 0;
 }