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authorYork Sun <yorksun@freescale.com>2012-10-08 07:44:31 +0000
committerAndy Fleming <afleming@freescale.com>2012-10-22 14:31:33 -0500
commit98ffa19053f2d10578a227de4e441698226fde0a (patch)
tree36010ca075f6ce2e62902c4b6321eff04f8cd5b4 /board
parentffd06e0231ac3fd0c5810f39f6e23527948df1c7 (diff)
powerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platform
New corenet platforms with chassis2 have separated DDR clock inputs. Use CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of detecting and displaying synchronous vs asynchronous mode. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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