ppc_4xx: Apply new HW register names

Modify all existing *.c files to use the new register names
as seen in the AMCC manuals.

Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>

28 files changed, 376 insertions, 376 deletions

diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 38186a5d378..2598f2cf41d 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -542,22 +542,22 @@ void pci_target_init(struct pci_controller *hose)
 	  |   Use byte reversed out routines to handle endianess.
 	  | Make this region non-prefetchable.
 	  +--------------------------------------------------------------------------*/
-	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
-
-	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
-	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
-
-	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
-	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
-	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
-	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */
+	out32r(PCIL0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIL0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIL0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+	out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIL0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIL0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
+	out32r(PCIL0_PTM1LA, 0);	/* Local Addr. Reg */
+	out32r(PCIL0_PTM2MS, 0);	/* Memory Size/Attribute */
+	out32r(PCIL0_PTM2LA, 0);	/* Local Addr. Reg */
 
 	/*--------------------------------------------------------------------------+
 	 * Set up Configuration registers
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 9495b621aca..91fae1917dd 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -339,27 +339,27 @@ void pci_target_init(struct pci_controller * hose )
 	/*
 	 * Disable everything
 	 */
-	out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
-	out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
-	out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
-	out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
+	out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
+	out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
+	out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
+	out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
 
 	/*
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 	 * strapping options to not support sizes such as 128/256 MB.
 	 */
-	out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-	out_le32((void *)PCIX0_PIM0LAH, 0);
-	out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
-	out_le32((void *)PCIX0_BAR0, 0);
+	out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+	out_le32((void *)PCIL0_PIM0LAH, 0);
+	out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
+	out_le32((void *)PCIL0_BAR0, 0);
 
 	/*
 	 * Program the board's subsystem id/vendor id
 	 */
-	out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-	out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+	out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
-	out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+	out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
 }
 #endif	/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
index e61b5de2d84..0ca1accec8d 100644
--- a/board/amcc/ebony/ebony.c
+++ b/board/amcc/ebony/ebony.c
@@ -210,28 +210,28 @@ void pci_target_init(struct pci_controller *hose)
 	/*--------------------------------------------------------------------------+
 	 * Disable everything
 	 *--------------------------------------------------------------------------*/
-	out32r(PCIX0_PIM0SA, 0);	/* disable */
-	out32r(PCIX0_PIM1SA, 0);	/* disable */
-	out32r(PCIX0_PIM2SA, 0);	/* disable */
-	out32r(PCIX0_EROMBA, 0);	/* disable expansion rom */
+	out32r(PCIL0_PIM0SA, 0);	/* disable */
+	out32r(PCIL0_PIM1SA, 0);	/* disable */
+	out32r(PCIL0_PIM2SA, 0);	/* disable */
+	out32r(PCIL0_EROMBA, 0);	/* disable expansion rom */
 
 	/*--------------------------------------------------------------------------+
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
      * options to not support sizes such as 128/256 MB.
 	 *--------------------------------------------------------------------------*/
-	out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-	out32r(PCIX0_PIM0LAH, 0);
-	out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+	out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+	out32r(PCIL0_PIM0LAH, 0);
+	out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
 
-	out32r(PCIX0_BAR0, 0);
+	out32r(PCIL0_BAR0, 0);
 
 	/*--------------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *--------------------------------------------------------------------------*/
-	out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-	out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+	out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
-	out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+	out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
 }
 #endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index aa6d0abddb8..908f1a5953c 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -305,27 +305,27 @@ void pci_target_init(struct pci_controller * hose )
 	/*-------------------------------------------------------------------+
 	 * Disable everything
 	 *-------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0SA, 0 ); /* disable */
-	out32r( PCIX0_PIM1SA, 0 ); /* disable */
-	out32r( PCIX0_PIM2SA, 0 ); /* disable */
-	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+	out32r( PCIL0_PIM0SA, 0 ); /* disable */
+	out32r( PCIL0_PIM1SA, 0 ); /* disable */
+	out32r( PCIL0_PIM2SA, 0 ); /* disable */
+	out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
 	/*-------------------------------------------------------------------+
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 	 * strapping options to not support sizes such as 128/256 MB.
 	 *-------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-	out32r( PCIX0_PIM0LAH, 0 );
-	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-	out32r( PCIX0_BAR0, 0 );
+	out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+	out32r( PCIL0_PIM0LAH, 0 );
+	out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+	out32r( PCIL0_BAR0, 0 );
 
 	/*-------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *-------------------------------------------------------------------*/
-	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+	out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+	out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+	out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
 }
 #endif	/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
diff --git a/board/amcc/luan/epld.h b/board/amcc/luan/epld.h
index 05362e06d78..569d78c4622 100644
--- a/board/amcc/luan/epld.h
+++ b/board/amcc/luan/epld.h
@@ -8,8 +8,8 @@
 #define EPLD0_FLASH_SRAM_SEL_N	0x01	/* 0 SRAM at mem top, 1 small flash at mem top */
 
 #define EPLD1_CLK_CNTL0		0x80	/* FSEL-FB1 of MPC9772 */
-#define EPLD1_PCIX0_CNTL1	0x40	/* S*0 of 9531 */
-#define EPLD1_PCIX0_CNTL2	0x20	/* S*1 of 9531 */
+#define EPLD1_PCIL0_CNTL1	0x40	/* S*0 of 9531 */
+#define EPLD1_PCIL0_CNTL2	0x20	/* S*1 of 9531 */
 #define EPLD1_CLK_CNTL3		0x10	/* FSEL-B1 of MPC9772 */
 #define EPLD1_CLK_CNTL4		0x08	/* FSEL-B0 of MPC9772 */
 #define EPLD1_MASTER_CLOCK6	0x04	/* clock source select 6 */
@@ -29,25 +29,25 @@
 #define EPLD3_STATUS_LED2	0x02	/* status LED 2 (1 = LED on) */
 #define EPLD3_STATUS_LED1	0x01	/* status LED 1 (1 = LED on) */
 
-#define EPLD4_PCIX0_VTH1	0x80	/* PCI-X 0 VTH1 status */
-#define EPLD4_PCIX0_VTH2	0x40	/* PCI-X 0 VTH2 status */
-#define EPLD4_PCIX0_VTH3	0x20	/* PCI-X 0 VTH3 status */
-#define EPLD4_PCIX0_VTH4	0x10	/* PCI-X 0 VTH4 status */
+#define EPLD4_PCIL0_VTH1	0x80	/* PCI-X 0 VTH1 status */
+#define EPLD4_PCIL0_VTH2	0x40	/* PCI-X 0 VTH2 status */
+#define EPLD4_PCIL0_VTH3	0x20	/* PCI-X 0 VTH3 status */
+#define EPLD4_PCIL0_VTH4	0x10	/* PCI-X 0 VTH4 status */
 #define EPLD4_PCIX1_VTH1	0x08	/* PCI-X 1 VTH1 status */
 #define EPLD4_PCIX1_VTH2	0x04	/* PCI-X 1 VTH2 status */
 #define EPLD4_PCIX1_VTH3	0x02	/* PCI-X 1 VTH3 status */
 #define EPLD4_PCIX1_VTH4	0x01	/* PCI-X 1 VTH4 status */
 
-#define EPLD5_PCIX0_INT0	0x80	/* PCIX0 INT0 status, write 0 to reset */
-#define EPLD5_PCIX0_INT1	0x40	/* PCIX0 INT1 status, write 0 to reset */
-#define EPLD5_PCIX0_INT2	0x20	/* PCIX0 INT2 status, write 0 to reset */
-#define EPLD5_PCIX0_INT3	0x10	/* PCIX0 INT3 status, write 0 to reset */
+#define EPLD5_PCIL0_INT0	0x80	/* PCIX0 INT0 status, write 0 to reset */
+#define EPLD5_PCIL0_INT1	0x40	/* PCIX0 INT1 status, write 0 to reset */
+#define EPLD5_PCIL0_INT2	0x20	/* PCIX0 INT2 status, write 0 to reset */
+#define EPLD5_PCIL0_INT3	0x10	/* PCIX0 INT3 status, write 0 to reset */
 #define EPLD5_PCIX1_INT0	0x08	/* PCIX1 INT0 status, write 0 to reset */
 #define EPLD5_PCIX1_INT1	0x04	/* PCIX1 INT1 status, write 0 to reset */
 #define EPLD5_PCIX1_INT2	0x02	/* PCIX1 INT2 status, write 0 to reset */
 #define EPLD5_PCIX1_INT3	0x01	/* PCIX1 INT3 status, write 0 to reset */
 
-#define EPLD6_PCIX0_RESET_CTL	0x80	/* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_PCIL0_RESET_CTL	0x80	/* 0=enable slot reset, 1=disable slot reset */
 #define EPLD6_PCIX1_RESET_CTL	0x40	/* 0=enable slot reset, 1=disable slot reset */
 #define EPLD6_ETH_INT_MODE	0x20	/* 0=IRQ5 recv's external eth int */
 #define EPLD6_PCIX2_RESET_CTL	0x10	/* 0=enable slot reset, 1=disable slot reset */
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index 5f76672fb52..a04f2af3b8d 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -173,28 +173,28 @@ void pci_target_init(struct pci_controller *hose)
 	/*--------------------------------------------------------------------------+
 	 * Disable everything
 	 *--------------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0SA, 0 ); /* disable */
-	out32r( PCIX0_PIM1SA, 0 ); /* disable */
-	out32r( PCIX0_PIM2SA, 0 ); /* disable */
-	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+	out32r( PCIL0_PIM0SA, 0 ); /* disable */
+	out32r( PCIL0_PIM1SA, 0 ); /* disable */
+	out32r( PCIL0_PIM2SA, 0 ); /* disable */
+	out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
 	/*--------------------------------------------------------------------------+
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 	 * options to not support sizes such as 128/256 MB.
 	 *--------------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-	out32r( PCIX0_PIM0LAH, 0 );
-	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+	out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+	out32r( PCIL0_PIM0LAH, 0 );
+	out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
-	out32r( PCIX0_BAR0, 0 );
+	out32r( PCIL0_BAR0, 0 );
 
 	/*--------------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *--------------------------------------------------------------------------*/
-	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+	out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+	out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+	out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
index d776edabcda..0aa317ec0e4 100644
--- a/board/amcc/ocotea/ocotea.c
+++ b/board/amcc/ocotea/ocotea.c
@@ -321,28 +321,28 @@ void pci_target_init(struct pci_controller * hose )
 	/*--------------------------------------------------------------------------+
 	 * Disable everything
 	 *--------------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0SA, 0 ); /* disable */
-	out32r( PCIX0_PIM1SA, 0 ); /* disable */
-	out32r( PCIX0_PIM2SA, 0 ); /* disable */
-	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+	out32r( PCIL0_PIM0SA, 0 ); /* disable */
+	out32r( PCIL0_PIM1SA, 0 ); /* disable */
+	out32r( PCIL0_PIM2SA, 0 ); /* disable */
+	out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
 	/*--------------------------------------------------------------------------+
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 	 * options to not support sizes such as 128/256 MB.
 	 *--------------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-	out32r( PCIX0_PIM0LAH, 0 );
-	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+	out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+	out32r( PCIL0_PIM0LAH, 0 );
+	out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
-	out32r( PCIX0_BAR0, 0 );
+	out32r( PCIL0_BAR0, 0 );
 
 	/*--------------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *--------------------------------------------------------------------------*/
-	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+	out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+	out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+	out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 17f831c3f41..d42c802538c 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -428,26 +428,26 @@ void pci_target_init(struct pci_controller *hose)
 	 * Use byte reversed out routines to handle endianess.
 	 * Make this region non-prefetchable.
 	 */
-	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
+	out32r(PCIL0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
 						/* - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, */
+	out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+	out32r(PCIL0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, */
 						/* and enable region */
 
-	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute */
+	out32r(PCIL0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute */
 						/* - disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
-	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, */
+	out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+	out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+	out32r(PCIL0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, */
 						/* and enable region */
 
-	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
-	out32r(PCIX0_PTM1LA, 0);		/* Local Addr. Reg */
-	out32r(PCIX0_PTM2MS, 0);		/* Memory Size/Attribute */
-	out32r(PCIX0_PTM2LA, 0);		/* Local Addr. Reg */
+	out32r(PCIL0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
+	out32r(PCIL0_PTM1LA, 0);		/* Local Addr. Reg */
+	out32r(PCIL0_PTM2MS, 0);		/* Memory Size/Attribute */
+	out32r(PCIL0_PTM2LA, 0);		/* Local Addr. Reg */
 
 	/*
 	 * Set up Configuration registers
diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c
index e4e441b319d..a9a80e5b6e3 100644
--- a/board/amcc/taishan/showinfo.c
+++ b/board/amcc/taishan/showinfo.c
@@ -39,13 +39,13 @@ void show_reset_reg(void)
 	mfcpr(CPR0_PLLD,reg);
 	printf("cpr_plld   = %#010lx\n",reg);
 
-	mfcpr(CPR0_PRIMAD,reg);
+	mfcpr(CPR0_PRIMAD0,reg);
 	printf("cpr_primad = %#010lx\n",reg);
 
-	mfcpr(CPR0_PRIMBD,reg);
+	mfcpr(CPR0_PRIMBD0,reg);
 	printf("cpr_primbd = %#010lx\n",reg);
 
-	mfcpr(CPR0_OPBD,reg);
+	mfcpr(CPR0_OPBD0,reg);
 	printf("cpr_opbd   = %#010lx\n",reg);
 
 	mfcpr(CPR0_PERD,reg);
@@ -106,59 +106,59 @@ void show_xbridge_info(void)
 	printf("SDR0_XPLLD  = %#010lx\n", reg);
 
 	printf("PCI-X Bridge Configure registers\n");
-	printf("PCIX0_VENDID            = %#06x\n", in16r(PCIX0_VENDID));
-	printf("PCIX0_DEVID             = %#06x\n", in16r(PCIX0_DEVID));
-	printf("PCIX0_CMD               = %#06x\n", in16r(PCIX0_CMD));
-	printf("PCIX0_STATUS            = %#06x\n", in16r(PCIX0_STATUS));
-	printf("PCIX0_REVID             = %#04x\n", in8(PCIX0_REVID));
-	printf("PCIX0_CACHELS           = %#04x\n", in8(PCIX0_CACHELS));
-	printf("PCIX0_LATTIM            = %#04x\n", in8(PCIX0_LATTIM));
-	printf("PCIX0_HDTYPE            = %#04x\n", in8(PCIX0_HDTYPE));
-	printf("PCIX0_BIST              = %#04x\n", in8(PCIX0_BIST));
-
-	printf("PCIX0_BAR0              = %#010lx\n", in32r(PCIX0_BAR0));
-	printf("PCIX0_BAR1              = %#010lx\n", in32r(PCIX0_BAR1));
-	printf("PCIX0_BAR2              = %#010lx\n", in32r(PCIX0_BAR2));
-	printf("PCIX0_BAR3              = %#010lx\n", in32r(PCIX0_BAR3));
-	printf("PCIX0_BAR4              = %#010lx\n", in32r(PCIX0_BAR4));
-	printf("PCIX0_BAR5              = %#010lx\n", in32r(PCIX0_BAR5));
-
-	printf("PCIX0_CISPTR            = %#010lx\n", in32r(PCIX0_CISPTR));
-	printf("PCIX0_SBSSYSVID         = %#010x\n", in16r(PCIX0_SBSYSVID));
-	printf("PCIX0_SBSSYSID          = %#010x\n", in16r(PCIX0_SBSYSID));
-	printf("PCIX0_EROMBA            = %#010lx\n", in32r(PCIX0_EROMBA));
-	printf("PCIX0_CAP               = %#04x\n", in8(PCIX0_CAP));
-	printf("PCIX0_INTLN             = %#04x\n", in8(PCIX0_INTLN));
-	printf("PCIX0_INTPN             = %#04x\n", in8(PCIX0_INTPN));
-	printf("PCIX0_MINGNT            = %#04x\n", in8(PCIX0_MINGNT));
-	printf("PCIX0_MAXLTNCY          = %#04x\n", in8(PCIX0_MAXLTNCY));
-
-	printf("PCIX0_BRDGOPT1          = %#010lx\n", in32r(PCIX0_BRDGOPT1));
-	printf("PCIX0_BRDGOPT2          = %#010lx\n", in32r(PCIX0_BRDGOPT2));
-
-	printf("PCIX0_POM0LAL           = %#010lx\n", in32r(PCIX0_POM0LAL));
-	printf("PCIX0_POM0LAH           = %#010lx\n", in32r(PCIX0_POM0LAH));
-	printf("PCIX0_POM0SA            = %#010lx\n", in32r(PCIX0_POM0SA));
-	printf("PCIX0_POM0PCILAL        = %#010lx\n", in32r(PCIX0_POM0PCIAL));
-	printf("PCIX0_POM0PCILAH        = %#010lx\n", in32r(PCIX0_POM0PCIAH));
-	printf("PCIX0_POM1LAL           = %#010lx\n", in32r(PCIX0_POM1LAL));
-	printf("PCIX0_POM1LAH           = %#010lx\n", in32r(PCIX0_POM1LAH));
-	printf("PCIX0_POM1SA            = %#010lx\n", in32r(PCIX0_POM1SA));
-	printf("PCIX0_POM1PCILAL        = %#010lx\n", in32r(PCIX0_POM1PCIAL));
-	printf("PCIX0_POM1PCILAH        = %#010lx\n", in32r(PCIX0_POM1PCIAH));
-	printf("PCIX0_POM2SA            = %#010lx\n", in32r(PCIX0_POM2SA));
-
-	printf("PCIX0_PIM0SA            = %#010lx\n", in32r(PCIX0_PIM0SA));
-	printf("PCIX0_PIM0LAL           = %#010lx\n", in32r(PCIX0_PIM0LAL));
-	printf("PCIX0_PIM0LAH           = %#010lx\n", in32r(PCIX0_PIM0LAH));
-	printf("PCIX0_PIM1SA            = %#010lx\n", in32r(PCIX0_PIM1SA));
-	printf("PCIX0_PIM1LAL           = %#010lx\n", in32r(PCIX0_PIM1LAL));
-	printf("PCIX0_PIM1LAH           = %#010lx\n", in32r(PCIX0_PIM1LAH));
-	printf("PCIX0_PIM2SA            = %#010lx\n", in32r(PCIX0_PIM1SA));
-	printf("PCIX0_PIM2LAL           = %#010lx\n", in32r(PCIX0_PIM1LAL));
-	printf("PCIX0_PIM2LAH           = %#010lx\n", in32r(PCIX0_PIM1LAH));
-
-	printf("PCIX0_XSTS              = %#010lx\n", in32r(PCIX0_STS));
+	printf("PCIL0_VENDID            = %#06x\n", in16r(PCIL0_VENDID));
+	printf("PCIL0_DEVID             = %#06x\n", in16r(PCIL0_DEVID));
+	printf("PCIL0_CMD               = %#06x\n", in16r(PCIL0_CMD));
+	printf("PCIL0_STATUS            = %#06x\n", in16r(PCIL0_STATUS));
+	printf("PCIL0_REVID             = %#04x\n", in8(PCIL0_REVID));
+	printf("PCIL0_CACHELS           = %#04x\n", in8(PCIL0_CACHELS));
+	printf("PCIL0_LATTIM            = %#04x\n", in8(PCIL0_LATTIM));
+	printf("PCIL0_HDTYPE            = %#04x\n", in8(PCIL0_HDTYPE));
+	printf("PCIL0_BIST              = %#04x\n", in8(PCIL0_BIST));
+
+	printf("PCIL0_BAR0              = %#010lx\n", in32r(PCIL0_BAR0));
+	printf("PCIL0_BAR1              = %#010lx\n", in32r(PCIL0_BAR1));
+	printf("PCIL0_BAR2              = %#010lx\n", in32r(PCIL0_BAR2));
+	printf("PCIL0_BAR3              = %#010lx\n", in32r(PCIL0_BAR3));
+	printf("PCIL0_BAR4              = %#010lx\n", in32r(PCIL0_BAR4));
+	printf("PCIL0_BAR5              = %#010lx\n", in32r(PCIL0_BAR5));
+
+	printf("PCIL0_CISPTR            = %#010lx\n", in32r(PCIL0_CISPTR));
+	printf("PCIL0_SBSSYSVID         = %#010x\n", in16r(PCIL0_SBSYSVID));
+	printf("PCIL0_SBSSYSID          = %#010x\n", in16r(PCIL0_SBSYSID));
+	printf("PCIL0_EROMBA            = %#010lx\n", in32r(PCIL0_EROMBA));
+	printf("PCIL0_CAP               = %#04x\n", in8(PCIL0_CAP));
+	printf("PCIL0_INTLN             = %#04x\n", in8(PCIL0_INTLN));
+	printf("PCIL0_INTPN             = %#04x\n", in8(PCIL0_INTPN));
+	printf("PCIL0_MINGNT            = %#04x\n", in8(PCIL0_MINGNT));
+	printf("PCIL0_MAXLTNCY          = %#04x\n", in8(PCIL0_MAXLTNCY));
+
+	printf("PCIL0_BRDGOPT1          = %#010lx\n", in32r(PCIL0_BRDGOPT1));
+	printf("PCIL0_BRDGOPT2          = %#010lx\n", in32r(PCIL0_BRDGOPT2));
+
+	printf("PCIL0_POM0LAL           = %#010lx\n", in32r(PCIL0_POM0LAL));
+	printf("PCIL0_POM0LAH           = %#010lx\n", in32r(PCIL0_POM0LAH));
+	printf("PCIL0_POM0SA            = %#010lx\n", in32r(PCIL0_POM0SA));
+	printf("PCIL0_POM0PCILAL        = %#010lx\n", in32r(PCIL0_POM0PCIAL));
+	printf("PCIL0_POM0PCILAH        = %#010lx\n", in32r(PCIL0_POM0PCIAH));
+	printf("PCIL0_POM1LAL           = %#010lx\n", in32r(PCIL0_POM1LAL));
+	printf("PCIL0_POM1LAH           = %#010lx\n", in32r(PCIL0_POM1LAH));
+	printf("PCIL0_POM1SA            = %#010lx\n", in32r(PCIL0_POM1SA));
+	printf("PCIL0_POM1PCILAL        = %#010lx\n", in32r(PCIL0_POM1PCIAL));
+	printf("PCIL0_POM1PCILAH        = %#010lx\n", in32r(PCIL0_POM1PCIAH));
+	printf("PCIL0_POM2SA            = %#010lx\n", in32r(PCIL0_POM2SA));
+
+	printf("PCIL0_PIM0SA            = %#010lx\n", in32r(PCIL0_PIM0SA));
+	printf("PCIL0_PIM0LAL           = %#010lx\n", in32r(PCIL0_PIM0LAL));
+	printf("PCIL0_PIM0LAH           = %#010lx\n", in32r(PCIL0_PIM0LAH));
+	printf("PCIL0_PIM1SA            = %#010lx\n", in32r(PCIL0_PIM1SA));
+	printf("PCIL0_PIM1LAL           = %#010lx\n", in32r(PCIL0_PIM1LAL));
+	printf("PCIL0_PIM1LAH           = %#010lx\n", in32r(PCIL0_PIM1LAH));
+	printf("PCIL0_PIM2SA            = %#010lx\n", in32r(PCIL0_PIM1SA));
+	printf("PCIL0_PIM2LAL           = %#010lx\n", in32r(PCIL0_PIM1LAL));
+	printf("PCIL0_PIM2LAH           = %#010lx\n", in32r(PCIL0_PIM1LAH));
+
+	printf("PCIL0_XSTS              = %#010lx\n", in32r(PCIL0_STS));
 }
 
 int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
index 4a0573eb380..0c20faf9ab6 100644
--- a/board/amcc/taishan/taishan.c
+++ b/board/amcc/taishan/taishan.c
@@ -254,28 +254,28 @@ void pci_target_init(struct pci_controller * hose )
 	/*--------------------------------------------------------------------------+
 	 * Disable everything
 	 *--------------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0SA, 0 ); /* disable */
-	out32r( PCIX0_PIM1SA, 0 ); /* disable */
-	out32r( PCIX0_PIM2SA, 0 ); /* disable */
-	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+	out32r( PCIL0_PIM0SA, 0 ); /* disable */
+	out32r( PCIL0_PIM1SA, 0 ); /* disable */
+	out32r( PCIL0_PIM2SA, 0 ); /* disable */
+	out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
 	/*--------------------------------------------------------------------------+
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 	 * options to not support sizes such as 128/256 MB.
 	 *--------------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-	out32r( PCIX0_PIM0LAH, 0 );
-	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+	out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+	out32r( PCIL0_PIM0LAH, 0 );
+	out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
-	out32r( PCIX0_BAR0, 0 );
+	out32r( PCIL0_BAR0, 0 );
 
 	/*--------------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *--------------------------------------------------------------------------*/
-	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+	out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+	out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+	out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 1ec13eb6b56..7ceccfa9b90 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -408,22 +408,22 @@ void pci_target_init(struct pci_controller *hose)
 	  |   Use byte reversed out routines to handle endianess.
 	  | Make this region non-prefetchable.
 	  +--------------------------------------------------------------------------*/
-	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
-
-	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
-
-	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
-	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
-	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
-	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */
+	out32r(PCIL0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIL0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIL0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 Local Address */
+	out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIL0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIL0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
+	out32r(PCIL0_PTM1LA, 0);	/* Local Addr. Reg */
+	out32r(PCIL0_PTM2MS, 0);	/* Memory Size/Attribute */
+	out32r(PCIL0_PTM2LA, 0);	/* Local Addr. Reg */
 
 	/*--------------------------------------------------------------------------+
 	 * Set up Configuration registers
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 5c9d49178cf..d8f4bcbb17d 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -633,27 +633,27 @@ void pci_target_init(struct pci_controller * hose )
 	/*-------------------------------------------------------------------+
 	 * Disable everything
 	 *-------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0SA, 0 ); /* disable */
-	out32r( PCIX0_PIM1SA, 0 ); /* disable */
-	out32r( PCIX0_PIM2SA, 0 ); /* disable */
-	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+	out32r( PCIL0_PIM0SA, 0 ); /* disable */
+	out32r( PCIL0_PIM1SA, 0 ); /* disable */
+	out32r( PCIL0_PIM2SA, 0 ); /* disable */
+	out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
 	/*-------------------------------------------------------------------+
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 	 * strapping options to not support sizes such as 128/256 MB.
 	 *-------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-	out32r( PCIX0_PIM0LAH, 0 );
-	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-	out32r( PCIX0_BAR0, 0 );
+	out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+	out32r( PCIL0_PIM0LAH, 0 );
+	out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+	out32r( PCIL0_BAR0, 0 );
 
 	/*-------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *-------------------------------------------------------------------*/
-	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+	out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+	out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+	out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
 }
 #endif	/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c
index 47e946f116a..eecae0a7fd1 100644
--- a/board/esd/common/cmd_loadpci.c
+++ b/board/esd/common/cmd_loadpci.c
@@ -48,7 +48,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	u32 la, ptm1la;
 
 #if defined(CONFIG_440)
-	ptm1la = in32r(PCIX0_PTM1LA);
+	ptm1la = in32r(PCIL0_PTM1LA);
 #else
 	ptm1la = in32r(PTM1LA);
 #endif
diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
index 056f455d687..d0e52cbab39 100644
--- a/board/esd/du440/du440.c
+++ b/board/esd/du440/du440.c
@@ -435,26 +435,26 @@ void pci_target_init(struct pci_controller *hose)
 	 * Use byte reversed out routines to handle endianess.
 	 * Make this region non-prefetchable.
 	 */
-	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
+	out32r(PCIL0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
 						/* - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, */
+	out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+	out32r(PCIL0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, */
 						/* and enable region */
 
-	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute */
+	out32r(PCIL0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute */
 						/* - disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
-	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, */
+	out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+	out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+	out32r(PCIL0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, */
 						/* and enable region */
 
-	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
-	out32r(PCIX0_PTM1LA, 0);		/* Local Addr. Reg */
-	out32r(PCIX0_PTM2MS, 0);		/* Memory Size/Attribute */
-	out32r(PCIX0_PTM2LA, 0);		/* Local Addr. Reg */
+	out32r(PCIL0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
+	out32r(PCIL0_PTM1LA, 0);		/* Local Addr. Reg */
+	out32r(PCIL0_PTM2MS, 0);		/* Memory Size/Attribute */
+	out32r(PCIL0_PTM2LA, 0);		/* Local Addr. Reg */
 
 	/*
 	 * Set up Configuration registers
diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c
index 1af431bd7d1..476e9409629 100644
--- a/board/esd/pmc440/cmd_pmc440.c
+++ b/board/esd/pmc440/cmd_pmc440.c
@@ -497,15 +497,15 @@ int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		/* map PCI address at 0xc0000000 in PLB space */
 
 		/* PMM1 Mask/Attribute - disabled b4 setting */
-		out32r(PCIX0_PMM1MA, 0x00000000);
+		out32r(PCIL0_PMM1MA, 0x00000000);
 		/* PMM1 Local Address */
-		out32r(PCIX0_PMM1LA, 0xc0000000);
+		out32r(PCIL0_PMM1LA, 0xc0000000);
 		/* PMM1 PCI Low Address */
-		out32r(PCIX0_PMM1PCILA, pciaddr);
+		out32r(PCIL0_PMM1PCILA, pciaddr);
 		/* PMM1 PCI High Address */
-		out32r(PCIX0_PMM1PCIHA, 0x00000000);
+		out32r(PCIL0_PMM1PCIHA, 0x00000000);
 		/* 256MB + No prefetching, and enable region */
-		out32r(PCIX0_PMM1MA, 0xf0000001);
+		out32r(PCIL0_PMM1MA, 0xf0000001);
 	} else {
 		printf("Usage:\npmm %s\n", cmdtp->help);
 	}
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index f0f9bff3eb2..ec9255243c4 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -208,7 +208,7 @@ int misc_init_f(void)
 
 	if (getenv("pciearly") && (!is_monarch())) {
 		printf("PCI:   early target init\n");
-		pci_setup_indirect(&hose, PCIX0_CFGADR, PCIX0_CFGDATA);
+		pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
 		pci_target_init(&hose);
 	}
 	return 0;
@@ -568,42 +568,42 @@ void pci_target_init(struct pci_controller *hose)
 	 * Use byte reversed out routines to handle endianess.
 	 * Make this region non-prefetchable.
 	 */
-	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
+	out32r(PCIL0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
 						/* - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM0MA, 0xc0000001);	/* 1G + No prefetching, */
+	out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+	out32r(PCIL0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM0MA, 0xc0000001);	/* 1G + No prefetching, */
 						/* and enable region */
 
 	if (!is_monarch()) {
 		ptmla_str = getenv("ptm1la");
 		ptmms_str = getenv("ptm1ms");
 		if(NULL != ptmla_str && NULL != ptmms_str ) {
-			out32r(PCIX0_PTM1MS,
+			out32r(PCIL0_PTM1MS,
 			       simple_strtoul(ptmms_str, NULL, 16));
-			out32r(PCIX0_PTM1LA,
+			out32r(PCIL0_PTM1LA,
 			       simple_strtoul(ptmla_str, NULL, 16));
 		} else {
 			/* BAR1: default top 64MB of RAM */
-			out32r(PCIX0_PTM1MS, 0xfc000001);
-			out32r(PCIX0_PTM1LA, 0x0c000000);
+			out32r(PCIL0_PTM1MS, 0xfc000001);
+			out32r(PCIL0_PTM1LA, 0x0c000000);
 		}
 	} else {
 		/* BAR1: default: complete 256MB RAM */
-		out32r(PCIX0_PTM1MS, 0xf0000001);
-		out32r(PCIX0_PTM1LA, 0x00000000);
+		out32r(PCIL0_PTM1MS, 0xf0000001);
+		out32r(PCIL0_PTM1LA, 0x00000000);
 	}
 
 	ptmla_str = getenv("ptm2la");		/* Local Addr. Reg */
 	ptmms_str = getenv("ptm2ms");		/* Memory Size/Attribute */
 	if(NULL != ptmla_str && NULL != ptmms_str ) {
-		out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
-		out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
+		out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
+		out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
 	} else {
 		/* BAR2: default: 4MB FPGA */
-		out32r(PCIX0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
-		out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */
+		out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
+		out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
 	}
 
 	if (is_monarch()) {
diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S
index 7a9726fe78e..721aaac3e74 100644
--- a/board/exbitgen/init.S
+++ b/board/exbitgen/init.S
@@ -52,7 +52,7 @@
 #define    IIC_EXTSTS	(I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
 #define    IIC_LSADR	(I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
 #define    IIC_HSADR	(I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
-#define    IIC_CLKDIV	(I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
+#define    IIC_CLKDIV	(I2C_REGISTERS_BASE_ADDRESS+IIC0_CLKDIV)
 #define    IIC_INTRMSK	(I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
 #define    IIC_XFRCNT	(I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
 #define    IIC_XTCNTLSS	(I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
@@ -537,7 +537,7 @@ read_spd:
 	WRITE_I2C(IICHSADR, 0x00)	/* clear hi slave address */
 	WRITE_I2C(IICSTS, 0x08)		/* update status register */
 	WRITE_I2C(IICEXTSTS, 0x8f)
-	WRITE_I2C(IICCLKDIV, 0x05)
+	WRITE_I2C(IIC0_CLKDIV, 0x05)
 	WRITE_I2C(IICINTRMSK, 0x00)	/* no interrupts */
 	WRITE_I2C(IICXFRCNT, 0x00)	/* clear transfer count */
 	WRITE_I2C(IICXTCNTLSS, 0xf0)	/* clear extended control & stat */
diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c
index 7cc1bf26783..90dbe52aa28 100644
--- a/board/gdsys/gdppc440etx/gdppc440etx.c
+++ b/board/gdsys/gdppc440etx/gdppc440etx.c
@@ -239,22 +239,22 @@ void pci_target_init(struct pci_controller *hose)
 	 *   Use byte reversed out routines to handle endianess.
 	 * Make this region non-prefetchable.
 	 */
-	out32r(PCIX0_PMM0MA, 0x00000000); 	/* disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
-	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
-	out32r(PCIX0_PMM0PCIHA, 0x00000000);
-	out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */
-
-	out32r(PCIX0_PMM1MA, 0x00000000);	/* disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
-	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
-	out32r(PCIX0_PMM1PCIHA, 0x00000000);
-	out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */
-
-	out32r(PCIX0_PTM1MS, 0x00000001);
-	out32r(PCIX0_PTM1LA, 0);
-	out32r(PCIX0_PTM2MS, 0);
-	out32r(PCIX0_PTM2LA, 0);
+	out32r(PCIL0_PMM0MA, 0x00000000); 	/* disabled b4 setting */
+	out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
+	out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
+	out32r(PCIL0_PMM0PCIHA, 0x00000000);
+	out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */
+
+	out32r(PCIL0_PMM1MA, 0x00000000);	/* disabled b4 setting */
+	out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
+	out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
+	out32r(PCIL0_PMM1PCIHA, 0x00000000);
+	out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */
+
+	out32r(PCIL0_PTM1MS, 0x00000001);
+	out32r(PCIL0_PTM1LA, 0);
+	out32r(PCIL0_PTM2MS, 0);
+	out32r(PCIL0_PTM2LA, 0);
 
 	/*
 	 * Set up Configuration registers
diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c
index 2cd2e6d4503..b42e90853f4 100644
--- a/board/gdsys/intip/intip.c
+++ b/board/gdsys/intip/intip.c
@@ -154,27 +154,27 @@ void pci_target_init(struct pci_controller *hose)
 	/*
 	 * Disable everything
 	 */
-	out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
-	out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
-	out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
-	out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
+	out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
+	out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
+	out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
+	out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
 
 	/*
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 	 * strapping options to not support sizes such as 128/256 MB.
 	 */
-	out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-	out_le32((void *)PCIX0_PIM0LAH, 0);
-	out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
-	out_le32((void *)PCIX0_BAR0, 0);
+	out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+	out_le32((void *)PCIL0_PIM0LAH, 0);
+	out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
+	out_le32((void *)PCIL0_BAR0, 0);
 
 	/*
 	 * Program the board's subsystem id/vendor id
 	 */
-	out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-	out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+	out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
-	out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+	out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
 }
 #endif	/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
diff --git a/board/korat/korat.c b/board/korat/korat.c
index 40a097cef59..8c674a20953 100644
--- a/board/korat/korat.c
+++ b/board/korat/korat.c
@@ -679,29 +679,29 @@ void pci_target_init(struct pci_controller *hose)
 	 * Use byte reversed out routines to handle endianess.
 	 * Make this region non-prefetchable.
 	 */
-	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
+	out32r(PCIL0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
 						/* - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA,
+	out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIL0_PMM0PCILA,
 	       CONFIG_SYS_PCI_MEMBASE);		/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, */
+	out32r(PCIL0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, */
 						/* and enable region */
 
-	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute */
+	out32r(PCIL0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute */
 						/* - disabled b4 setting */
-	out32r(PCIX0_PMM1LA,
+	out32r(PCIL0_PMM1LA,
 	       CONFIG_SYS_PCI_MEMBASE + 0x20000000);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM1PCILA,
+	out32r(PCIL0_PMM1PCILA,
 	       CONFIG_SYS_PCI_MEMBASE + 0x20000000);	/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, */
+	out32r(PCIL0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, */
 						/* and enable region */
 
-	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
-	out32r(PCIX0_PTM1LA, 0);		/* Local Addr. Reg */
-	out32r(PCIX0_PTM2MS, 0);		/* Memory Size/Attribute */
-	out32r(PCIX0_PTM2LA, 0);		/* Local Addr. Reg */
+	out32r(PCIL0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
+	out32r(PCIL0_PTM1LA, 0);		/* Local Addr. Reg */
+	out32r(PCIL0_PTM2MS, 0);		/* Memory Size/Attribute */
+	out32r(PCIL0_PTM2LA, 0);		/* Local Addr. Reg */
 
 	/*
 	 * Set up Configuration registers
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index f4090f40dd3..ef7f2e8dc57 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -351,22 +351,22 @@ void pci_target_init(struct pci_controller *hose)
 	  |   Use byte reversed out routines to handle endianess.
 	  | Make this region non-prefetchable.
 	  +--------------------------------------------------------------------------*/
-	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
-
-	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
-	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
-
-	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
-	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
-	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
-	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */
+	out32r(PCIL0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIL0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIL0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+	out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIL0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIL0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
+	out32r(PCIL0_PTM1LA, 0);	/* Local Addr. Reg */
+	out32r(PCIL0_PTM2MS, 0);	/* Memory Size/Attribute */
+	out32r(PCIL0_PTM2LA, 0);	/* Local Addr. Reg */
 
 	/*--------------------------------------------------------------------------+
 	 * Set up Configuration registers
diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
index 4522612daef..946c3f3a4dd 100644
--- a/board/netstal/hcu5/hcu5.c
+++ b/board/netstal/hcu5/hcu5.c
@@ -398,27 +398,27 @@ void pci_target_init(struct pci_controller *hose)
 	 * Make this region non-prefetchable.
 	 */
 	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM0MA, 0x00000000);
-	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIL0_PMM0MA, 0x00000000);
+	out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
 	/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
-	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
+	out32r(PCIL0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	/* 512M + No prefetching, and enable region */
-	out32r(PCIX0_PMM0MA, 0xE0000001);
+	out32r(PCIL0_PMM0MA, 0xE0000001);
 
 	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM1MA, 0x00000000);
-	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 Local Address */
+	out32r(PCIL0_PMM1MA, 0x00000000);
+	out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 Local Address */
 	/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
-	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
+	out32r(PCIL0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	/* 512M + No prefetching, and enable region */
-	out32r(PCIX0_PMM1MA, 0xE0000001);
+	out32r(PCIL0_PMM1MA, 0xE0000001);
 
-	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
-	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
-	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
-	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */
+	out32r(PCIL0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
+	out32r(PCIL0_PTM1LA, 0);	/* Local Addr. Reg */
+	out32r(PCIL0_PTM2MS, 0);	/* Memory Size/Attribute */
+	out32r(PCIL0_PTM2LA, 0);	/* Local Addr. Reg */
 
 	/*
 	 * Set up Configuration registers
diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
index ac059a903b1..b70827e0cc2 100644
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -626,22 +626,22 @@ void pci_target_init(struct pci_controller *hose)
 	  |   Use byte reversed out routines to handle endianess.
 	  | Make this region non-prefetchable.
 	  +--------------------------------------------------------------------------*/
-	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
-
-	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
-
-	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
-	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
-	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
-	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */
+	out32r(PCIL0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIL0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIL0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 Local Address */
+	out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIL0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIL0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
+	out32r(PCIL0_PTM1LA, 0);	/* Local Addr. Reg */
+	out32r(PCIL0_PTM2MS, 0);	/* Memory Size/Attribute */
+	out32r(PCIL0_PTM2LA, 0);	/* Local Addr. Reg */
 
 	/*--------------------------------------------------------------------------+
 	 * Set up Configuration registers
diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c
index cdb91ac36b4..51335c4d9c8 100644
--- a/board/prodrive/alpr/alpr.c
+++ b/board/prodrive/alpr/alpr.c
@@ -192,28 +192,28 @@ void pci_target_init(struct pci_controller * hose )
 	/*--------------------------------------------------------------------------+
 	 * Disable everything
 	 *--------------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0SA, 0 ); /* disable */
-	out32r( PCIX0_PIM1SA, 0 ); /* disable */
-	out32r( PCIX0_PIM2SA, 0 ); /* disable */
-	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+	out32r( PCIL0_PIM0SA, 0 ); /* disable */
+	out32r( PCIL0_PIM1SA, 0 ); /* disable */
+	out32r( PCIL0_PIM2SA, 0 ); /* disable */
+	out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
 	/*--------------------------------------------------------------------------+
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 	 * options to not support sizes such as 128/256 MB.
 	 *--------------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-	out32r( PCIX0_PIM0LAH, 0 );
-	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+	out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+	out32r( PCIL0_PIM0LAH, 0 );
+	out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
-	out32r( PCIX0_BAR0, 0 );
+	out32r( PCIL0_BAR0, 0 );
 
 	/*--------------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *--------------------------------------------------------------------------*/
-	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+	out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+	out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+	out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
@@ -270,21 +270,21 @@ void pci_master_init(struct pci_controller *hose)
 	  |   Use byte reversed out routines to handle endianess.
 	  | Make this region non-prefetchable.
 	  +--------------------------------------------------------------------------*/
-	out32r( PCIX0_POM0SA, 0 ); /* disable */
-	out32r( PCIX0_POM1SA, 0 ); /* disable */
-	out32r( PCIX0_POM2SA, 0 ); /* disable */
-
-	out32r(PCIX0_POM0LAL, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_POM0LAH, 0x00000003);	/* PMM0 Local Address */
-	out32r(PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
-	out32r(PCIX0_POM0PCIAH, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1);	/* 256MB + enable region */
-
-	out32r(PCIX0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 Local Address */
-	out32r(PCIX0_POM1LAH, 0x00000003);	/* PMM0 Local Address */
-	out32r(PCIX0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
-	out32r(PCIX0_POM1PCIAH, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1);	/* 256MB + enable region */
+	out32r( PCIL0_POM0SA, 0 ); /* disable */
+	out32r( PCIL0_POM1SA, 0 ); /* disable */
+	out32r( PCIL0_POM2SA, 0 ); /* disable */
+
+	out32r(PCIL0_POM0LAL, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIL0_POM0LAH, 0x00000003);	/* PMM0 Local Address */
+	out32r(PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIL0_POM0PCIAH, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_POM0SA, ~(0x10000000 - 1) | 1);	/* 256MB + enable region */
+
+	out32r(PCIL0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 Local Address */
+	out32r(PCIL0_POM1LAH, 0x00000003);	/* PMM0 Local Address */
+	out32r(PCIL0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIL0_POM1PCIAH, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIL0_POM1SA, ~(0x10000000 - 1) | 1);	/* 256MB + enable region */
 }
 #endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
 
diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c
index 20fd4dc2769..9a078527609 100644
--- a/board/prodrive/p3p440/p3p440.c
+++ b/board/prodrive/p3p440/p3p440.c
@@ -209,28 +209,28 @@ void pci_target_init(struct pci_controller *hose)
 	/*--------------------------------------------------------------------------+
 	 * Disable everything
 	 *--------------------------------------------------------------------------*/
-	out32r(PCIX0_PIM0SA, 0);	/* disable */
-	out32r(PCIX0_PIM1SA, 0);	/* disable */
-	out32r(PCIX0_PIM2SA, 0);	/* disable */
-	out32r(PCIX0_EROMBA, 0);	/* disable expansion rom */
+	out32r(PCIL0_PIM0SA, 0);	/* disable */
+	out32r(PCIL0_PIM1SA, 0);	/* disable */
+	out32r(PCIL0_PIM2SA, 0);	/* disable */
+	out32r(PCIL0_EROMBA, 0);	/* disable expansion rom */
 
 	/*--------------------------------------------------------------------------+
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 	 * options to not support sizes such as 128/256 MB.
 	 *--------------------------------------------------------------------------*/
-	out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-	out32r(PCIX0_PIM0LAH, 0);
-	out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+	out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+	out32r(PCIL0_PIM0LAH, 0);
+	out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
 
-	out32r(PCIX0_BAR0, 0);
+	out32r(PCIL0_BAR0, 0);
 
 	/*--------------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *--------------------------------------------------------------------------*/
-	out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-	out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+	out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
-	out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+	out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
 }
 #endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
diff --git a/board/sandburst/common/ppc440gx_i2c.h b/board/sandburst/common/ppc440gx_i2c.h
index 328abd64b89..90f27caa0da 100644
--- a/board/sandburst/common/ppc440gx_i2c.h
+++ b/board/sandburst/common/ppc440gx_i2c.h
@@ -44,7 +44,7 @@
 #define    IIC_EXTSTS1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICEXTSTS)
 #define    IIC_LSADR1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLSADR)
 #define    IIC_HSADR1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHSADR)
-#define    IIC_CLKDIV1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCLKDIV)
+#define    IIC_CLKDIV1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IIC0_CLKDIV)
 #define    IIC_INTRMSK1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICINTRMSK)
 #define    IIC_XFRCNT1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXFRCNT)
 #define    IIC_XTCNTLSS1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXTCNTLSS)
diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c
index e1c61463dd2..a484874ea35 100644
--- a/board/sandburst/common/sb_common.c
+++ b/board/sandburst/common/sb_common.c
@@ -346,28 +346,28 @@ void pci_target_init(struct pci_controller * hose )
 	/*--------------------------------------------------------------------------+
 	 * Disable everything
 	 *--------------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0SA, 0 ); /* disable */
-	out32r( PCIX0_PIM1SA, 0 ); /* disable */
-	out32r( PCIX0_PIM2SA, 0 ); /* disable */
-	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+	out32r( PCIL0_PIM0SA, 0 ); /* disable */
+	out32r( PCIL0_PIM1SA, 0 ); /* disable */
+	out32r( PCIL0_PIM2SA, 0 ); /* disable */
+	out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
 
 	/*--------------------------------------------------------------------------+
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 	 * options to not support sizes such as 128/256 MB.
 	 *--------------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-	out32r( PCIX0_PIM0LAH, 0 );
-	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+	out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
+	out32r( PCIL0_PIM0LAH, 0 );
+	out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
-	out32r( PCIX0_BAR0, 0 );
+	out32r( PCIL0_BAR0, 0 );
 
 	/*--------------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *--------------------------------------------------------------------------*/
-	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+	out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+	out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
-	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+	out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
diff --git a/board/xes/xpedite1000/xpedite1000.c b/board/xes/xpedite1000/xpedite1000.c
index 011fb94bb63..04949bb2d46 100644
--- a/board/xes/xpedite1000/xpedite1000.c
+++ b/board/xes/xpedite1000/xpedite1000.c
@@ -156,7 +156,7 @@ int pci_pre_init(struct pci_controller * hose)
 		return 0;
 
 #if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
-	/* Setup System Device Register PCIX0_XCR */
+	/* Setup System Device Register PCIL0_XCR */
 	mfsdr(SDR0_XCR, strap);
 	strap &= 0x0f000000;
 	mtsdr(SDR0_XCR, strap);
@@ -175,26 +175,26 @@ int pci_pre_init(struct pci_controller * hose)
 void pci_target_init(struct pci_controller * hose)
 {
 	/* Disable everything */
-	out32r(PCIX0_PIM0SA, 0);
-	out32r(PCIX0_PIM1SA, 0);
-	out32r(PCIX0_PIM2SA, 0);
-	out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
+	out32r(PCIL0_PIM0SA, 0);
+	out32r(PCIL0_PIM1SA, 0);
+	out32r(PCIL0_PIM2SA, 0);
+	out32r(PCIL0_EROMBA, 0); /* disable expansion rom */
 
 	/*
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 	 * options to not support sizes such as 128/256 MB.
 	 */
-	out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
-	out32r(PCIX0_PIM0LAH, 0);
-	out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+	out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+	out32r(PCIL0_PIM0LAH, 0);
+	out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
 
-	out32r(PCIX0_BAR0, 0);
+	out32r(PCIL0_BAR0, 0);
 
 	/* Program the board's subsystem id/vendor id */
-	out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
-	out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
+	out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
-	out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+	out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
 }
 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */