diff options
| author | Haiying Wang <Haiying.Wang@freescale.com> | 2009-05-20 12:30:33 -0400 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-06-12 00:11:10 -0500 |
| commit | b2aab386e957ba684d4f2a466bfaa91770e5058a (patch) | |
| tree | db39460fff5f61772c16cff15cf6c180d288240f /board | |
| parent | 399b53cbab0b377ac4c5c16c19c6e41b68a9c719 (diff) | |
85xx: Add UART1 support for MPC8569MDS
MPC8569 UART1 signals are muxed with PortF bit[9-12], we need to define
those pins before using UART1.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mpc8569mds/mpc8569mds.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 129c58c5f73..7e6cfb73733 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -77,6 +77,12 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */ {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */ + /* UART1 is muxed with QE PortF bit [9-12].*/ + {5, 12, 2, 0, 3}, /* UART1_SIN */ + {5, 9, 1, 0, 3}, /* UART1_SOUT */ + {5, 10, 2, 0, 3}, /* UART1_CTS_B */ + {5, 11, 1, 0, 2}, /* UART1_RTS_B */ + {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ }; |