Merge with /home/m8/git/u-boot

17 files changed, 128 insertions, 64 deletions

diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c
index e847879b167..24c6f0d9869 100644
--- a/board/csb272/csb272.c
+++ b/board/csb272/csb272.c
@@ -164,10 +164,15 @@ long initdram (int board_type)
 int last_stage_init(void)
 {
 	/* initialize the PHY */
-	miiphy_reset(CONFIG_PHY_ADDR);
-	miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR,
-			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);	/* AUTO neg */
-	miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);	/* LEDs     */
+	miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
+
+	/* AUTO neg */
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+
+	/* LEDs     */
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);
+
 
 	return 0; /* success */
 }
diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c
index 83418dac8c1..833bbce923d 100644
--- a/board/csb472/csb472.c
+++ b/board/csb472/csb472.c
@@ -132,10 +132,14 @@ long initdram (int board_type)
 int last_stage_init(void)
 {
 	/* initialize the PHY */
-	miiphy_reset(CONFIG_PHY_ADDR);
-	miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR,
-			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);	/* AUTO neg */
-	miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);	/* LEDs     */
+	miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
+
+	/* AUTO neg */
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+
+	/* LEDs     */
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);
 
 	return 0; /* success */
 }
diff --git a/board/esd/common/misc.c b/board/esd/common/misc.c
index cba8c92f2e5..48b4b7c7b96 100644
--- a/board/esd/common/misc.c
+++ b/board/esd/common/misc.c
@@ -33,8 +33,8 @@ void lxt971_no_sleep(void)
 {
 	unsigned short reg;
 
-	miiphy_read(CONFIG_PHY_ADDR, 0x10, &reg);
+	miiphy_read("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, &reg);
 	reg &= ~0x0040;                  /* disable sleep mode */
-	miiphy_write(CONFIG_PHY_ADDR, 0x10, reg);
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, reg);
 }
 #endif /* CONFIG_LXT971_NO_SLEEP */
diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c
index a248cadf73c..eafa48bc6ea 100644
--- a/board/evb64260/eth.c
+++ b/board/evb64260/eth.c
@@ -85,12 +85,17 @@ static const char ether_port_phy_addr[3]={0,1,2};
 static const char ether_port_phy_addr[3]={4,5,6};
 #endif
 
+/* MII PHY access routines are common for all i/f, use gal_ent0 */
+#define GT6426x_MII_DEVNAME	"gal_enet0"
+
+int gt6426x_miiphy_read(char *devname, unsigned char phy,
+		unsigned char reg, unsigned short *val);
 
 static inline unsigned short
 miiphy_read_ret(unsigned short phy, unsigned short reg)
 {
     unsigned short val;
-    miiphy_read(phy,reg,&val);
+    gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val);
     return val;
 }
 
@@ -339,8 +344,8 @@ gt6426x_eth_disable(void *v)
 MII utilities - write: write to an MII register via SMI
 ***************************************************************************/
 int
-miiphy_write(unsigned char phy, unsigned char reg,
-    unsigned short data)
+gt6426x_miiphy_write(char *devname, unsigned char phy,
+		unsigned char reg, unsigned short data)
 {
     unsigned int temp= (reg<<21) | (phy<<16) | data;
 
@@ -354,8 +359,8 @@ miiphy_write(unsigned char phy, unsigned char reg,
 MII utilities - read: read from an MII register via SMI
 ***************************************************************************/
 int
-miiphy_read(unsigned char phy, unsigned char reg,
-			unsigned short *val)
+gt6426x_miiphy_read(char *devname, unsigned char phy,
+		unsigned char reg, unsigned short *val)
 {
     unsigned int temp= (reg<<21) | (phy<<16) | 1<<26;
 
@@ -444,7 +449,7 @@ check_phy_state(struct eth_dev_s *p)
 		if ((psr & 0x3) != want) {
 			printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n",
 					psr & 0x3, want);
-			miiphy_write(ether_port_phy_addr[p->dev],0,
+			miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0,
 					miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9));
 			udelay(10000);	/* the EVB's GT takes a while to notice phy
 					   went down and up */
@@ -490,7 +495,7 @@ gt6426x_eth_probe(void *v, bd_t *bis)
 	   led 2: 0xc=link/rxact
 	   led 3: 0x2=rxact (N/C)
 	   strch: 0,2=30 ms, enable */
-	miiphy_write(ether_port_phy_addr[p->dev], 20, 0x1c22);
+	miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22);
 
 	/* 2.7ns port rise time */
 	/*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */
@@ -792,6 +797,11 @@ gt6426x_eth_initialize(bd_t *bis)
 
 
 		eth_register(dev);
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+		miiphy_register(dev->name,
+				gt6426x_miiphy_read, gt6426x_miiphy_write);
+#endif
 	}
+
 }
 #endif /* CFG_CMD_NET && CONFIG_NET_MULTI */
diff --git a/board/funkwerk/vovpn-gw/m88e6060.c b/board/funkwerk/vovpn-gw/m88e6060.c
index e4ff3c37c50..03a03d0af09 100644
--- a/board/funkwerk/vovpn-gw/m88e6060.c
+++ b/board/funkwerk/vovpn-gw/m88e6060.c
@@ -160,12 +160,12 @@ m88e6060_initialize( int devAddr )
 
 	/*** reset all phys into powerdown ************************************/
 	for (i=0, err=0; i<M88X_PHY_CNT; i++) {
-		err += miiphy_read( devAddr+phyTab[i],M88X_PHY_CNTL,&val );
+		err += bb_miiphy_read(NULL, devAddr+phyTab[i],M88X_PHY_CNTL,&val );
 		/* keep SpeedLSB, Duplex */
 		val &= 0x2100;
 		/* set SWReset, AnegEn, PwrDwn, RestartAneg */
 		val |= 0x9a00;
-		err += miiphy_write( devAddr+phyTab[i],M88X_PHY_CNTL,val );
+		err += bb_miiphy_write(NULL, devAddr+phyTab[i],M88X_PHY_CNTL,val );
 	}
 	if (err) {
 		printf( "%s [ERR] reset phys\n",_f );
@@ -174,9 +174,9 @@ m88e6060_initialize( int devAddr )
 
 	/*** disable all ports ************************************************/
 	for (i=0, err=0; i<M88X_PRT_CNT; i++) {
-		err += miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val );
+		err += bb_miiphy_read(NULL, devAddr+prtTab[i],M88X_PRT_CNTL,&val );
 		val &= 0xfffc;
-		err += miiphy_write( devAddr+prtTab[i],M88X_PRT_CNTL,val );
+		err += bb_miiphy_write(NULL, devAddr+prtTab[i],M88X_PRT_CNTL,val );
 	}
 	if (err) {
 		printf( "%s [ERR] disable ports\n",_f );
@@ -187,33 +187,33 @@ m88e6060_initialize( int devAddr )
 	/* set switch mac addr */
 #define ea eth_get_dev()->enetaddr
 	val = (ea[4] <<  8) | ea[5];
-	err = miiphy_write( devAddr+15,M88X_GLB_MAC45,val );
+	err = bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC45,val );
 	val = (ea[2] <<  8) | ea[3];
-	err += miiphy_write( devAddr+15,M88X_GLB_MAC23,val );
+	err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC23,val );
 	val = (ea[0] <<  8) | ea[1];
 #undef ea
 	val &= 0xfeff;		/* clear DiffAddr */
-	err += miiphy_write( devAddr+15,M88X_GLB_MAC01,val );
+	err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC01,val );
 	if (err) {
 		printf( "%s [ERR] switch mac address register\n",_f );
 		return( -1 );
 	}
 
 	/* !DiscardExcessive, MaxFrameSize, CtrMode */
-	err = miiphy_read( devAddr+15,M88X_GLB_CNTL,&val );
+	err = bb_miiphy_read(NULL, devAddr+15,M88X_GLB_CNTL,&val );
 	val &= 0xd870;
 	val |= 0x0500;
-	err += miiphy_write( devAddr+15,M88X_GLB_CNTL,val );
+	err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_CNTL,val );
 	if (err) {
 		printf( "%s [ERR] switch global control register\n",_f );
 		return( -1 );
 	}
 
 	/* LernDis off, ATUSize 1024, AgeTime 5min */
-	err = miiphy_read( devAddr+15,M88X_ATU_CNTL,&val );
+	err = bb_miiphy_read(NULL, devAddr+15,M88X_ATU_CNTL,&val );
 	val &= 0x000f;
 	val |= 0x2130;
-	err += miiphy_write( devAddr+15,M88X_ATU_CNTL,val );
+	err += bb_miiphy_write(NULL, devAddr+15,M88X_ATU_CNTL,val );
 	if (err) {
 		printf( "%s [ERR] atu control register\n",_f );
 		return( -1 );
@@ -226,10 +226,10 @@ m88e6060_initialize( int devAddr )
 		}
 		while (p->reg != -1) {
 			err = 0;
-			err += miiphy_read( devAddr+prtTab[i],p->reg,&val );
+			err += bb_miiphy_read(NULL, devAddr+prtTab[i],p->reg,&val );
 			val &= p->msk;
 			val |= p->val;
-			err += miiphy_write( devAddr+prtTab[i],p->reg,val );
+			err += bb_miiphy_write(NULL, devAddr+prtTab[i],p->reg,val );
 			if (err) {
 				printf( "%s [ERR] config port %d register %d\n",_f,i,p->reg );
 				/* XXX what todo */
@@ -245,10 +245,10 @@ m88e6060_initialize( int devAddr )
 		}
 		while (p->reg != -1) {
 			err = 0;
-			err += miiphy_read( devAddr+phyTab[i],p->reg,&val );
+			err += bb_miiphy_read(NULL, devAddr+phyTab[i],p->reg,&val );
 			val &= p->msk;
 			val |= p->val;
-			err += miiphy_write( devAddr+phyTab[i],p->reg,val );
+			err += bb_miiphy_write(NULL, devAddr+phyTab[i],p->reg,val );
 			if (err) {
 				printf( "%s [ERR] config phy %d register %d\n",_f,i,p->reg );
 				/* XXX what todo */
diff --git a/board/funkwerk/vovpn-gw/vovpn-gw.c b/board/funkwerk/vovpn-gw/vovpn-gw.c
index 4acddefa508..97f81eefcfd 100644
--- a/board/funkwerk/vovpn-gw/vovpn-gw.c
+++ b/board/funkwerk/vovpn-gw/vovpn-gw.c
@@ -198,7 +198,7 @@ void reset_phy (void)
 	iop->pdat |= 0x00080000;
 	for (i=0; i<100; i++) {
 		udelay(20000);
-		if (miiphy_read( CFG_PHY_ADDR,2,&val ) == 0) {
+		if (bb_miiphy_read("FCC1 ETHERNET", CFG_PHY_ADDR,2,&val ) == 0) {
 			break;
 		}
 	}
diff --git a/board/mpc8260ads/mpc8260ads.c b/board/mpc8260ads/mpc8260ads.c
index a1d0a08e97f..374e97961bd 100644
--- a/board/mpc8260ads/mpc8260ads.c
+++ b/board/mpc8260ads/mpc8260ads.c
@@ -238,8 +238,9 @@ void reset_phy (void)
 	 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
 	 * Enable autonegotiation.
 	 */
-	miiphy_write(CFG_PHY_ADDR, 16, 0x610);
-	miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+	bb_miiphy_write(NULL, CFG_PHY_ADDR, 16, 0x610);
+	bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 #else
 	/*
 	 * Ethernet PHY is configured (by means of configuration pins)
@@ -247,9 +248,15 @@ void reset_phy (void)
 	 * to advertise all capabilities, including 100Mb/s, and
 	 * restart autonegotiation.
 	 */
-	miiphy_write(CFG_PHY_ADDR, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
-	miiphy_write(CFG_PHY_ADDR, PHY_DCR,  0x0000); /* Do not bypass Rx/Tx (de)scrambler */
-	miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+
+	/* Advertise all capabilities */
+	bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E1);
+	
+	/* Do not bypass Rx/Tx (de)scrambler */
+	bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_DCR,  0x0000);
+
+	bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
 #endif /* CONFIG_MII */
 }
diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c
index 9accc5cd333..25f69a0bf5d 100644
--- a/board/mpc8560ads/mpc8560ads.c
+++ b/board/mpc8560ads/mpc8560ads.c
@@ -237,9 +237,14 @@ void reset_phy (void)
 	udelay(1000);
 #endif
 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
-	miiphy_reset(0x0);	/* reset PHY */
-	miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
-	miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+	/* reset PHY */
+	miiphy_reset("FCC1 ETHERNET", 0x0);
+
+	/* change PHY address to 0x02 */
+	bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
+
+	bb_miiphy_write(NULL, 0x02, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 #endif /* CONFIG_MII */
 }
 
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index 84d3e1ed5c1..9c469b09ac9 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -731,12 +731,12 @@ int last_stage_init (void)
 	char *s;
 	mem_test_reloc();
 	/* write correct LED configuration */
-	if (miiphy_write (0x1, 0x14, 0x2402) != 0) {
+	if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
 		printf ("Error writing to the PHY\n");
 	}
 	/* since LED/CFG2 is not connected on the -2,
 	 * write to correct capability information */
-	if (miiphy_write (0x1, 0x4, 0x01E1) != 0) {
+	if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) {
 		printf ("Error writing to the PHY\n");
 	}
 	print_mip405_rev ();
diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c
index 698115a3191..dd03e4bd5bd 100644
--- a/board/netphone/netphone.c
+++ b/board/netphone/netphone.c
@@ -38,6 +38,11 @@
 #include <watchdog.h>
 #endif
 
+int fec8xx_miiphy_read(char *devname, unsigned char addr,
+		unsigned char  reg, unsigned short *value);
+int fec8xx_miiphy_write(char *devname, unsigned char  addr,
+		unsigned char  reg, unsigned short value);
+
 /****************************************************************/
 
 /* some sane bit macros */
@@ -483,12 +488,13 @@ void reset_phys(void)
 	mii_init();
 
 	for (phyno = 0; phyno < 32; ++phyno) {
-		miiphy_read(phyno, PHY_PHYIDR1, &v);
+		fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
 		if (v == 0xFFFF)
 			continue;
-		miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
+		fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
 		udelay(10000);
-		miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
+		fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
+				PHY_BMCR_RESET | PHY_BMCR_AUTON);
 		udelay(10000);
 	}
 }
diff --git a/board/netta/netta.c b/board/netta/netta.c
index e7024e52d3c..9194bfb9de3 100644
--- a/board/netta/netta.c
+++ b/board/netta/netta.c
@@ -35,6 +35,11 @@
 #include <watchdog.h>
 #endif
 
+int fec8xx_miiphy_read(char *devname, unsigned char addr,
+		unsigned char  reg, unsigned short *value);
+int fec8xx_miiphy_write(char *devname, unsigned char  addr,
+		unsigned char  reg, unsigned short value);
+
 /****************************************************************/
 
 /* some sane bit macros */
@@ -431,12 +436,13 @@ void reset_phys(void)
 	mii_init();
 
 	for (phyno = 0; phyno < 32; ++phyno) {
-		miiphy_read(phyno, PHY_PHYIDR1, &v);
+		fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
 		if (v == 0xFFFF)
 			continue;
-		miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
+		fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
 		udelay(10000);
-		miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
+		fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
+				PHY_BMCR_RESET | PHY_BMCR_AUTON);
 		udelay(10000);
 	}
 }
diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c
index f4ce7a4946e..c9b405145e5 100644
--- a/board/netta2/netta2.c
+++ b/board/netta2/netta2.c
@@ -36,6 +36,11 @@
 #include <watchdog.h>
 #endif
 
+int fec8xx_miiphy_read(char *devname, unsigned char addr,
+		unsigned char  reg, unsigned short *value);
+int fec8xx_miiphy_write(char *devname, unsigned char  addr,
+		unsigned char  reg, unsigned short value);
+
 /****************************************************************/
 
 /* some sane bit macros */
@@ -481,12 +486,13 @@ void reset_phys(void)
 	mii_init();
 
 	for (phyno = 0; phyno < 32; ++phyno) {
-		miiphy_read(phyno, PHY_PHYIDR1, &v);
+		fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
 		if (v == 0xFFFF)
 			continue;
-		miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
+		fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
 		udelay(10000);
-		miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
+		fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
+				PHY_BMCR_RESET | PHY_BMCR_AUTON);
 		udelay(10000);
 	}
 }
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
index 7f7272da1f7..e8b9929e771 100644
--- a/board/sbc8560/sbc8560.c
+++ b/board/sbc8560/sbc8560.c
@@ -223,9 +223,14 @@ void reset_phy (void)
 	udelay(1000);
 #endif
 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
-	miiphy_reset(0x0);	/* reset PHY */
-	miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
-	miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+	/* reset PHY */
+	miiphy_reset("FCC1 ETHERNET", 0x0);
+
+	/* change PHY address to 0x02 */
+	bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
+
+	bb_miiphy_write(NULL, 0x02, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 #endif /* CONFIG_MII */
 }
 
diff --git a/board/stxgp3/stxgp3.c b/board/stxgp3/stxgp3.c
index 1dd9b2f17bc..2b3949cd7b3 100644
--- a/board/stxgp3/stxgp3.c
+++ b/board/stxgp3/stxgp3.c
@@ -239,9 +239,14 @@ reset_phy(void)
 	udelay(1000);
 #endif
 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
-	miiphy_reset(0x0);	/* reset PHY */
-	miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
-	miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+	/* reset PHY */
+	miiphy_reset("FCC1 ETHERNET", 0x0);
+
+	/* change PHY address to 0x02 */
+	bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
+
+	bb_miiphy_write(NULL, 0x02, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 #endif /* CONFIG_MII */
 #endif
 }
diff --git a/board/stxxtc/stxxtc.c b/board/stxxtc/stxxtc.c
index b38b4bea474..aa3d129f9c9 100644
--- a/board/stxxtc/stxxtc.c
+++ b/board/stxxtc/stxxtc.c
@@ -481,12 +481,12 @@ void reset_phys(void)
 	mii_init();
 
 	for (phyno = 0; phyno < 32; ++phyno) {
-		miiphy_read(phyno, PHY_PHYIDR1, &v);
+		miiphy_read("FEC ETHERNET", phyno, PHY_PHYIDR1, &v);
 		if (v == 0xFFFF)
 			continue;
-		miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
+		miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_POWD);
 		udelay(10000);
-		miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
+		miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
 		udelay(10000);
 	}
 }
diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c
index b25928cf1fe..056e562bfea 100644
--- a/board/trab/auto_update.c
+++ b/board/trab/auto_update.c
@@ -199,7 +199,7 @@ extern int transfer_pic(unsigned char, unsigned char *, int, int);
 #endif
 extern int flash_sect_erase(ulong, ulong);
 extern int flash_sect_protect (int, ulong, ulong);
-extern int flash_write (uchar *, ulong, ulong);
+extern int flash_write (char *, ulong, ulong);
 /* change char* to void* to shutup the compiler */
 extern int i2c_write_multiple (uchar, uint, int, void *, int);
 extern int i2c_read_multiple (uchar, uint, int, void *, int);
diff --git a/board/uc100/uc100.c b/board/uc100/uc100.c
index 1387b93ffcb..4f2cff624fe 100644
--- a/board/uc100/uc100.c
+++ b/board/uc100/uc100.c
@@ -30,6 +30,8 @@
 #include <i2c.h>
 #include <miiphy.h>
 
+int fec8xx_miiphy_write(char *devname, unsigned char  addr,
+		unsigned char  reg, unsigned short value);
 
 /*********************************************************************/
 /* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B)     */
@@ -258,8 +260,11 @@ int misc_init_r (void)
 	 */
 	mii_init();
 
-	miiphy_write(0, PHY_BMCR, 0x2100);    /* disable auto-negotiation, 100mbit, full-duplex */
-	miiphy_write(0, PHY_FCSCR, 0x4122);   /* set LED's to Link, Transmit, Receive           */
+	/* disable auto-negotiation, 100mbit, full-duplex */
+	fec8xx_miiphy_write(NULL, 0, PHY_BMCR, 0x2100);
+
+	/* set LED's to Link, Transmit, Receive           */
+	fec8xx_miiphy_write(NULL,  0, PHY_FCSCR, 0x4122);
 
 	return 0;
 }