diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2011-11-03 10:55:28 -0700 |
|---|---|---|
| committer | Stefan Reinauer <reinauer@chromium.org> | 2011-11-03 14:52:31 -0700 |
| commit | f749f16593e24eaddb3c11017429b2c0751ddf18 (patch) | |
| tree | 0acfe817dede8de23fd289c016cdac9bb46dace4 /board | |
| parent | ff7f9647c491066feedd8dcee9c7c3b0fd466394 (diff) | |
Clean up MTRR 7 right before jumping to the kernel
This cleans up the rom caching optimization implemented in coreboot (and
needed throughout u-boot runtime.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
BUG=chrome-os-partner:6585
TEST=boot coreboot on stumpy
Change-Id: I7242c9c2b0546c633be8fb8ebc815ed6e6fda4d1
Reviewed-on: https://gerrit.chromium.org/gerrit/11138
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'board')
| -rw-r--r-- | board/chromebook-x86/coreboot/coreboot.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/board/chromebook-x86/coreboot/coreboot.c b/board/chromebook-x86/coreboot/coreboot.c index 9f7d6e091a1..dace515ea46 100644 --- a/board/chromebook-x86/coreboot/coreboot.c +++ b/board/chromebook-x86/coreboot/coreboot.c @@ -38,6 +38,8 @@ #include <chromeos/cros_gpio.h> #include <chromeos/common.h> #include <asm/io.h> +#include <asm/msr.h> +#include <asm/cache.h> #include <coreboot/timestamp.h> #ifdef CONFIG_HW_WATCHDOG #include <watchdog.h> @@ -190,6 +192,22 @@ int board_i8042_skip(void) return fdt_decode_get_config_int(gd->blob, "skip-i8042", 0); } +#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) +#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) + +int board_final_cleanup(void) +{ + /* Un-cache the ROM so the kernel has one + * more MTRR available. + */ + disable_cache(); + wrmsr(MTRRphysBase_MSR(7), 0); + wrmsr(MTRRphysMask_MSR(7), 0); + enable_cache(); + + return 0; +} + #ifdef CONFIG_HW_WATCHDOG void hw_watchdog_reset(void) { |