mt_ventoux: remove board

This board still doesn't select CONFIG_DM and seems to be umaintained.
As it makes progress on modernizing several DaVinci drivers more
difficult and the maintainer has not expressed interest in updating
it, this patch proposes to remove it.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: Stefano Babic <sbabic@denx.de>

5 files changed, 0 insertions, 770 deletions

diff --git a/board/teejet/mt_ventoux/Kconfig b/board/teejet/mt_ventoux/Kconfig
deleted file mode 100644
index fd7196a6f91..00000000000
--- a/board/teejet/mt_ventoux/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MT_VENTOUX
-
-config SYS_BOARD
-	default "mt_ventoux"
-
-config SYS_VENDOR
-	default "teejet"
-
-config SYS_CONFIG_NAME
-	default "mt_ventoux"
-
-endif
diff --git a/board/teejet/mt_ventoux/MAINTAINERS b/board/teejet/mt_ventoux/MAINTAINERS
deleted file mode 100644
index d23464c20f8..00000000000
--- a/board/teejet/mt_ventoux/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MT_VENTOUX BOARD
-M:	Stefano Babic <sbabic@denx.de>
-S:	Maintained
-F:	board/teejet/mt_ventoux/
-F:	include/configs/mt_ventoux.h
-F:	configs/mt_ventoux_defconfig
diff --git a/board/teejet/mt_ventoux/Makefile b/board/teejet/mt_ventoux/Makefile
deleted file mode 100644
index f0071562866..00000000000
--- a/board/teejet/mt_ventoux/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
-#
-# Based on ti/evm/Makefile
-
-obj-y	:= mt_ventoux.o
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c
deleted file mode 100644
index 33de7a21318..00000000000
--- a/board/teejet/mt_ventoux/mt_ventoux.c
+++ /dev/null
@@ -1,342 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright (C) 2009 TechNexion Ltd.
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <malloc.h>
-#include <fpga.h>
-#include <video_fb.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/omap_gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/dss.h>
-#include <asm/arch/clock.h>
-#include <i2c.h>
-#include <spartan3.h>
-#include <asm/gpio.h>
-#ifdef CONFIG_USB_EHCI_HCD
-#include <usb.h>
-#include <asm/ehci-omap.h>
-#endif
-#include "mt_ventoux.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define BUZZER		140
-#define SPEAKER		141
-#define USB1_PWR	127
-#define USB2_PWR	149
-
-#ifndef CONFIG_FPGA
-#error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
-#endif
-
-#define FPGA_RESET	62
-#define FPGA_PROG	116
-#define FPGA_CCLK	117
-#define FPGA_DIN	118
-#define FPGA_INIT	119
-#define FPGA_DONE	154
-
-#define LCD_PWR		138
-#define LCD_PON_PIN	139
-
-#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
-static struct {
-	u32 xres;
-	u32 yres;
-} panel_resolution[] = {
-	{ 480, 272 },
-	{ 800, 480 }
-};
-
-static struct panel_config lcd_cfg[] = {
-	{
-	.timing_h       = PANEL_TIMING_H(40, 5, 2),
-	.timing_v       = PANEL_TIMING_V(8, 8, 2),
-	.pol_freq       = 0x00003000, /* Pol Freq */
-	.divisor        = 0x00010033, /* 9 Mhz Pixel Clock */
-	.panel_type     = 0x01, /* TFT */
-	.data_lines     = 0x03, /* 24 Bit RGB */
-	.load_mode      = 0x02, /* Frame Mode */
-	.panel_color	= 0,
-	.gfx_format	= GFXFORMAT_RGB24_UNPACKED,
-	},
-	{
-	.timing_h       = PANEL_TIMING_H(20, 192, 4),
-	.timing_v       = PANEL_TIMING_V(2, 20, 10),
-	.pol_freq       = 0x00004000, /* Pol Freq */
-	.divisor        = 0x0001000E, /* 36Mhz Pixel Clock */
-	.panel_type     = 0x01, /* TFT */
-	.data_lines     = 0x03, /* 24 Bit RGB */
-	.load_mode      = 0x02, /* Frame Mode */
-	.panel_color	= 0,
-	.gfx_format	= GFXFORMAT_RGB24_UNPACKED,
-	}
-};
-#endif
-
-/* Timing definitions for FPGA */
-static const u32 gpmc_fpga[] = {
-	FPGA_GPMC_CONFIG1,
-	FPGA_GPMC_CONFIG2,
-	FPGA_GPMC_CONFIG3,
-	FPGA_GPMC_CONFIG4,
-	FPGA_GPMC_CONFIG5,
-	FPGA_GPMC_CONFIG6,
-};
-
-#ifdef CONFIG_USB_EHCI_HCD
-static struct omap_usbhs_board_data usbhs_bdata = {
-	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
-		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-	return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
-}
-
-int ehci_hcd_stop(int index)
-{
-	return omap_ehci_hcd_stop();
-}
-#endif
-
-
-static inline void fpga_reset(int nassert)
-{
-	gpio_set_value(FPGA_RESET, !nassert);
-}
-
-int fpga_pgm_fn(int nassert, int nflush, int cookie)
-{
-	debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__);
-
-	gpio_set_value(FPGA_PROG, !nassert);
-
-	return nassert;
-}
-
-int fpga_init_fn(int cookie)
-{
-	return !gpio_get_value(FPGA_INIT);
-}
-
-int fpga_done_fn(int cookie)
-{
-	return gpio_get_value(FPGA_DONE);
-}
-
-int fpga_pre_config_fn(int cookie)
-{
-	debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
-
-	/* Setting GPIOs for programming Mode */
-	gpio_request(FPGA_RESET, "FPGA_RESET");
-	gpio_direction_output(FPGA_RESET, 1);
-	gpio_request(FPGA_PROG, "FPGA_PROG");
-	gpio_direction_output(FPGA_PROG, 1);
-	gpio_request(FPGA_CCLK, "FPGA_CCLK");
-	gpio_direction_output(FPGA_CCLK, 1);
-	gpio_request(FPGA_DIN, "FPGA_DIN");
-	gpio_direction_output(FPGA_DIN, 0);
-	gpio_request(FPGA_INIT, "FPGA_INIT");
-	gpio_direction_input(FPGA_INIT);
-	gpio_request(FPGA_DONE, "FPGA_DONE");
-	gpio_direction_input(FPGA_DONE);
-
-	/* Be sure that signal are deasserted */
-	gpio_set_value(FPGA_RESET, 1);
-	gpio_set_value(FPGA_PROG, 1);
-
-	return 0;
-}
-
-int fpga_post_config_fn(int cookie)
-{
-	debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__);
-
-	fpga_reset(true);
-	udelay(100);
-	fpga_reset(false);
-
-	return 0;
-}
-
-/* Write program to the FPGA */
-int fpga_wr_fn(int nassert_write, int flush, int cookie)
-{
-	gpio_set_value(FPGA_DIN, nassert_write);
-
-	return nassert_write;
-}
-
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
-	gpio_set_value(FPGA_CCLK, assert_clk);
-
-	return assert_clk;
-}
-
-xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = {
-	fpga_pre_config_fn,
-	fpga_pgm_fn,
-	fpga_clk_fn,
-	fpga_init_fn,
-	fpga_done_fn,
-	fpga_wr_fn,
-	fpga_post_config_fn,
-};
-
-xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
-			(void *)&mt_ventoux_fpga_fns, 0);
-
-/* Initialize the FPGA */
-static void mt_ventoux_init_fpga(void)
-{
-	fpga_pre_config_fn(0);
-
-	/* Setting CS1 for FPGA access */
-	enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1],
-		FPGA_BASE_ADDR, GPMC_SIZE_128M);
-
-	fpga_init();
-	fpga_add(fpga_xilinx, &fpga);
-}
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
-	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-	mt_ventoux_init_fpga();
-
-	/* GPIO_140: speaker #mute */
-	MUX_VAL(CP(MCBSP3_DX),		(IEN | PTU | EN | M4))
-	/* GPIO_141: Buzz Hi */
-	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTU | EN | M4))
-
-	/* Turning off the buzzer */
-	gpio_request(BUZZER, "BUZZER_MUTE");
-	gpio_request(SPEAKER, "SPEAKER");
-	gpio_direction_output(BUZZER, 0);
-	gpio_direction_output(SPEAKER, 0);
-
-	/* Activate USB power */
-	gpio_request(USB1_PWR, "USB1_PWR");
-	gpio_request(USB2_PWR, "USB2_PWR");
-	gpio_direction_output(USB1_PWR, 1);
-	gpio_direction_output(USB2_PWR, 1);
-
-	return 0;
-}
-
-#ifndef CONFIG_SPL_BUILD
-int misc_init_r(void)
-{
-	char *eth_addr;
-	struct tam3517_module_info info;
-	int ret;
-
-	TAM3517_READ_EEPROM(&info, ret);
-	omap_die_id_display();
-
-	if (ret)
-		return 0;
-	eth_addr = env_get("ethaddr");
-	if (!eth_addr)
-		TAM3517_READ_MAC_FROM_EEPROM(&info);
-
-	TAM3517_PRINT_SOM_INFO(&info);
-	return 0;
-}
-#endif
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *		hardware. Many pins need to be moved from protect to primary
- *		mode.
- */
-void set_muxconf_regs(void)
-{
-	MUX_MT_VENTOUX();
-}
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int board_eth_init(bd_t *bis)
-{
-	davinci_emac_initialize();
-	return 0;
-}
-
-#if defined(CONFIG_MMC_OMAP_HS) && \
-	!defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
-{
-	return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
-int board_video_init(void)
-{
-	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-	struct panel_config *panel = &lcd_cfg[0];
-	char *s;
-	u32 index = 0;
-
-	void *fb;
-
-	fb = (void *)0x88000000;
-
-	s = env_get("panel");
-	if (s) {
-		index = simple_strtoul(s, NULL, 10);
-		if (index < ARRAY_SIZE(lcd_cfg))
-			panel = &lcd_cfg[index];
-		else
-			return 0;
-	}
-
-	panel->frame_buffer = fb;
-	printf("Panel: %dx%d\n", panel_resolution[index].xres,
-		panel_resolution[index].yres);
-	panel->lcd_size = (panel_resolution[index].yres - 1) << 16 |
-		(panel_resolution[index].xres - 1);
-
-	gpio_request(LCD_PWR, "LCD Power");
-	gpio_request(LCD_PON_PIN, "LCD Pon");
-	gpio_direction_output(LCD_PWR, 0);
-	gpio_direction_output(LCD_PON_PIN, 1);
-
-
-	setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
-	setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
-
-	omap3_dss_panel_config(panel);
-	omap3_dss_enable();
-
-	return 0;
-}
-#endif
diff --git a/board/teejet/mt_ventoux/mt_ventoux.h b/board/teejet/mt_ventoux/mt_ventoux.h
deleted file mode 100644
index 5e017742340..00000000000
--- a/board/teejet/mt_ventoux/mt_ventoux.h
+++ /dev/null
@@ -1,403 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Stefano Babic <sbabic@denx.de>
- *
- * Author: Hardy Weng <hardy.weng@technexion.com>
- *
- * Copyright (C) 2010 TechNexion Ltd.
- */
-
-#ifndef _MT_VENTOUX_H_
-#define _MT_VENTOUX_H_
-
-const omap3_sysinfo sysinfo = {
-	DDR_DISCRETE,
-	"Teejet MT_VENTOUX Board",
-	"NAND",
-};
-
-/* FPGA CS1 configuration */
-#define FPGA_GPMC_CONFIG1	0x00001200
-#define FPGA_GPMC_CONFIG2	0x00161f00
-#define FPGA_GPMC_CONFIG3	0x00040400
-#define FPGA_GPMC_CONFIG4	0x120c1f08
-#define FPGA_GPMC_CONFIG5	0x001e161f
-#define FPGA_GPMC_CONFIG6	0x96080fcf
-
-#define FPGA_BASE_ADDR		0x20000000
-
-/*
- * IEN  - Input Enable
- * IDIS - Input Disable
- * PTD  - Pull type Down
- * PTU  - Pull type Up
- * DIS  - Pull type selection is inactive
- * EN	- Pull type selection is active
- * M0	- Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_MT_VENTOUX() \
-	/* SDRC */\
-	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SDRC_DQS0N),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SDRC_DQS1N),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SDRC_DQS2N),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SDRC_DQS3N),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SDRC_CKE0),		(M0)) \
-	MUX_VAL(CP(SDRC_CKE1),		(M0)) \
-	MUX_VAL(CP(STRBEN_DLY0),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(STRBEN_DLY1),	(IEN  | PTD | EN  | M0)) \
-	/* GPMC */\
-	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS1),		(IEN | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTD | EN  | M4))/* GPIO 53 */\
-	MUX_VAL(CP(GPMC_NCS3),		(IEN | PTU | EN | M4))	/* GPIO 54 */\
-	MUX_VAL(CP(GPMC_NCS4),		(IEN | PTD | EN | M4)) \
-			/* GPIO 55 : NFS */\
-	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_NCS6),		(IDIS  | PTD | EN | M3)) /*PWM11*/ \
-	MUX_VAL(CP(GPMC_NCS7),		(IDIS  | PTD | EN | M4)) /*GPIO_58*/ \
-	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M4)) \
-			/*GPIO_62: FPGA_RESET */ \
-	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) \
-			/* GPIO_64*/ \
-	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M4)) \
-	/* DSS */\
-	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) \
-	/* CAMERA */\
-	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) \
-	/* MMC */\
-	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M4)) \
-			/* GPIO_126: CardDetect */\
-	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) \
-			/*GPIO_128 */ \
-	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) \
-	\
-	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN | M0)) /*MMC2_CLK*/\
-	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | DIS  | M0)) /*MMC2_CMD*/\
-	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT0*/\
-	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT1*/\
-	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT2*/\
-	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | DIS  | M0)) /*MMC2_DAT3*/\
-	MUX_VAL(CP(MMC2_DAT4),		(IDIS  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MMC2_DAT5),		(IDIS  | PTU | EN  | M4)) \
-	MUX_VAL(CP(MMC2_DAT6),		(IDIS  | PTU | EN  | M4)) \
-			/* GPIO_138: LCD_ENVD */\
-	MUX_VAL(CP(MMC2_DAT7),		(IDIS  | PTD | EN  | M4)) \
-			/* GPIO_139: LCD_PON */\
-	/* McBSP */\
-	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M0)) \
-	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) \
-	\
-	MUX_VAL(CP(MCBSP2_FSX),		(IEN | PTD | EN | M4)) \
-			/* GPIO_116: FPGA_PROG */ \
-	MUX_VAL(CP(MCBSP2_CLKX),	(IEN | PTD | EN | M4)) \
-			/* GPIO_117: FPGA_CCLK */ \
-	MUX_VAL(CP(MCBSP2_DR),		(IEN | PTD | EN | M4)) \
-			/* GPIO_118: FPGA_DIN */ \
-	MUX_VAL(CP(MCBSP2_DX),		(IEN | PTD | EN | M4)) \
-			/* GPIO_119: FPGA_INIT */ \
-	\
-	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTU | EN | M4)) \
-	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTU | EN | M4)) \
-	\
-	MUX_VAL(CP(MCBSP4_CLKX),	(IEN | PTD | DIS | M4)) \
-			/*GPIO_152: Ignition Sense */ \
-	MUX_VAL(CP(MCBSP4_DR),		(IEN | PTD | DIS | M4)) \
-			/*GPIO_153: Power Button Sense */ \
-	MUX_VAL(CP(MCBSP4_DX),		(IEN | PTU | DIS | M4)) \
-			/* GPIO_154: FPGA_DONE */ \
-	MUX_VAL(CP(MCBSP4_FSX),		(IEN | PTD | DIS | M4)) \
-			/* GPIO_155: CA8_irq */ \
-	/* UART */\
-	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART1_RTS),		(IEN | PTU | EN | M4)) \
-			/* GPIO_149: USB status 2 */\
-	MUX_VAL(CP(UART1_CTS),		(IEN | PTU | EN | M4)) \
-			/* GPIO_150: USB status 1 */\
-	\
-	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M2)) \
-			/* gpt9_pwm */\
-	MUX_VAL(CP(UART2_RTS),		(IEN | PTD | DIS | M2)) \
-			/* gpt10_pwm */\
-	MUX_VAL(CP(UART2_TX),		(IEN | PTD | DIS | M2)) \
-			/* gpt8_pwm */\
-	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M2)) \
-			/* gpt11_pwm */\
-	\
-	MUX_VAL(CP(UART3_CTS_RCTX),	(IDIS  | PTD | DIS | M4)) \
-			/*GPIO_163 : TS_PENIRQ*/ \
-	MUX_VAL(CP(UART3_RTS_SD),	(IEN | PTD | DIS | M4)) \
-			/*GPIO_164 : MMC */\
-	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) \
-	/* I2C */\
-	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) \
-	/* McSPI */\
-	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(MCSPI1_CS1),		(IEN | PTD | EN | M4)) /*GPIO_175*/\
-	MUX_VAL(CP(MCSPI1_CS2),		(IEN | PTD | EN | M4)) /*GPIO_176*/\
-	MUX_VAL(CP(MCSPI1_CS3),		(IEN | PTD | EN | M4)) \
-	\
-	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M4)) \
-	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M0)) \
-	/* CCDC */\
-	MUX_VAL(CP(CCDC_PCLK),		(IEN  | PTU | EN  | M4)) \
-			/* GPIO94 */\
-	MUX_VAL(CP(CCDC_FIELD),		(IEN  | PTD | DIS | M4)) \
-			/* GPIO95: #Enable Output */\
-	MUX_VAL(CP(CCDC_HD),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(CCDC_VD),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(CCDC_WEN),		(IEN  | PTD | DIS | M4)) \
-			/* GPIO 99: #SOM_PWR_OFF */\
-	MUX_VAL(CP(CCDC_DATA0),		(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(CCDC_DATA1),		(IEN  | PTD | DIS | M4)) \
-			/* GPIO_100: #power out */\
-	MUX_VAL(CP(CCDC_DATA2),		(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(CCDC_DATA3),		(IEN  | PTD | DIS | M4)) \
-			/* GPIO_102 */\
-	MUX_VAL(CP(CCDC_DATA4),		(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(CCDC_DATA5),		(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(CCDC_DATA6),		(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(CCDC_DATA7),		(IEN  | PTD | DIS | M4)) \
-	/* RMII */\
-	MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  |  M0)) \
-	MUX_VAL(CP(RMII_MDIO_CLK),	(M0)) \
-	MUX_VAL(CP(RMII_RXD0)	,	(IEN  | PTD | M0)) \
-	MUX_VAL(CP(RMII_RXD1),		(IEN  | PTD | M0)) \
-	MUX_VAL(CP(RMII_CRS_DV),	(IEN  | PTD | M0)) \
-	MUX_VAL(CP(RMII_RXER),		(PTD | M0)) \
-	MUX_VAL(CP(RMII_TXD0),		(PTD | M0)) \
-	MUX_VAL(CP(RMII_TXD1),		(PTD | M0)) \
-	MUX_VAL(CP(RMII_TXEN),		(PTD | M0)) \
-	MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTD | EN  | M0)) \
-	/* HECC */\
-	MUX_VAL(CP(HECC1_TXD),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(HECC1_RXD),		(IEN  | PTU | EN  | M0)) \
-	/* HSUSB */\
-	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_STP),		(IEN  | PTU | DIS  | M0)) \
-	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTU | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(USB0_DRVBUS),	(IEN  | PTD | EN  | M0)) \
-	/* HDQ */\
-	MUX_VAL(CP(HDQ_SIO),		(IEN | PTD | EN | M4)) \
-			/* GPIO_170: auto update */\
-	/* Control and debug */\
-	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(SYS_NRESWARM),	(IDIS | PTU | DIS | M4)) \
-			/* - GPIO30 */\
-	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
-	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3 */\
-	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4*/\
-	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
-	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
-	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
-	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/\
-	MUX_VAL(CP(SYS_BOOT7),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(SYS_BOOT8),		(IEN  | PTD | EN  | M0)) \
-	\
-	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_CLKOUT1),	(IDIS | PTD | DIS | M4)) \
-			/* gpio_10 */\
-	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) \
-	/* JTAG */\
-	MUX_VAL(CP(JTAG_NTRST),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(JTAG_EMU0),		(IDIS  | PTD | EN | M4)) /*GPIO_11*/ \
-	MUX_VAL(CP(JTAG_EMU1),		(IDIS  | PTD | EN | M4)) /*GPIO_31*/ \
-	/* ETK (ES2 onwards) */\
-	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTD | DIS  | M3)) \
-					/* hsusb1_stp */ \
-	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M3)) \
-					/* hsusb1_clk */\
-	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTU | EN  | M3)) \
-	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTU | EN  | M3)) \
-	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTU | EN  | M3)) \
-	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | EN  | M3)) \
-	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | EN  | M3)) \
-	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | EN  | M3)) \
-	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | EN  | M3)) \
-	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | EN  | M3)) \
-	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | EN  | M3)) \
-	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | EN  | M3)) \
-	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTD | EN  | M4)) \
-					/* gpio_24 */\
-	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTD | DIS | M4)) \
-	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M4)) \
-					/* gpio_26 */\
-	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M3)) \
-	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M4)) \
-	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M4)) \
-					/* gpio_29 */\
-	/* Die to Die */\
-	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) \
-	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) \
-
-#endif