Merge branch 'master' of git://git.denx.de/u-boot-sunxi

- Convert DM_MMC and DM_SCSI
- A20, R40, H6 Linux dts(i) sync
- CLK, RESET support for sunxi, sun8_emac net drivers

3 files changed, 0 insertions, 145 deletions

diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index 4d6258d932..c4e13f8c38 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -8,9 +8,6 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 obj-y	+= board.o
 obj-$(CONFIG_SUN7I_GMAC)	+= gmac.o
-ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_SUNXI_AHCI)	+= ahci.o
-endif
 obj-$(CONFIG_MACH_SUN4I)	+= dram_sun4i_auto.o
 obj-$(CONFIG_MACH_SUN5I)	+= dram_sun5i_auto.o
 obj-$(CONFIG_MACH_SUN7I)	+= dram_sun5i_auto.o
diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c
deleted file mode 100644
index a79b80ca1e..0000000000
--- a/board/sunxi/ahci.c
+++ /dev/null
@@ -1,134 +0,0 @@
-#include <common.h>
-#include <ahci.h>
-#include <dm.h>
-#include <scsi.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-
-#define AHCI_PHYCS0R 0x00c0
-#define AHCI_PHYCS1R 0x00c4
-#define AHCI_PHYCS2R 0x00c8
-#define AHCI_RWCR    0x00fc
-
-/* This magic PHY initialisation was taken from the Allwinner releases
- * and Linux driver, but is completely undocumented.
- */
-static int sunxi_ahci_phy_init(u8 *reg_base)
-{
-	u32 reg_val;
-	int timeout;
-
-	writel(0, reg_base + AHCI_RWCR);
-	mdelay(5);
-
-	setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19);
-	clrsetbits_le32(reg_base + AHCI_PHYCS0R,
-			(0x7 << 24),
-			(0x5 << 24) | (0x1 << 23) | (0x1 << 18));
-	clrsetbits_le32(reg_base + AHCI_PHYCS1R,
-			(0x3 << 16) | (0x1f << 8) | (0x3 << 6),
-			(0x2 << 16) | (0x6 << 8) | (0x2 << 6));
-	setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15));
-	clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19));
-	clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20));
-	clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5));
-	mdelay(5);
-
-	setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19));
-
-	timeout = 250; /* Power up takes approx 50 us */
-	for (;;) {
-		reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28);
-		if (reg_val == (0x2 << 28))
-			break;
-		if (--timeout == 0) {
-			printf("AHCI PHY power up failed.\n");
-			return -EIO;
-		}
-		udelay(1);
-	};
-
-	setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24));
-
-	timeout = 100; /* Calibration takes approx 10 us */
-	for (;;) {
-		reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24);
-		if (reg_val == 0x0)
-			break;
-		if (--timeout == 0) {
-			printf("AHCI PHY calibration failed.\n");
-			return -EIO;
-		}
-		udelay(1);
-	}
-
-	mdelay(15);
-
-	writel(0x7, reg_base + AHCI_RWCR);
-
-	return 0;
-}
-
-#ifndef CONFIG_DM_SCSI
-void scsi_init(void)
-{
-	if (sunxi_ahci_phy_init((u8 *)SUNXI_SATA_BASE) < 0)
-		return;
-
-	ahci_init((void __iomem *)SUNXI_SATA_BASE);
-}
-#else
-static int sunxi_sata_probe(struct udevice *dev)
-{
-	ulong base;
-	u8 *reg;
-	int ret;
-
-	base = dev_read_addr(dev);
-	if (base == FDT_ADDR_T_NONE) {
-		debug("%s: Failed to find address (err=%d\n)", __func__, ret);
-		return -EINVAL;
-	}
-	reg = (u8 *)base;
-	ret = sunxi_ahci_phy_init(reg);
-	if (ret) {
-		debug("%s: Failed to init phy (err=%d\n)", __func__, ret);
-		return ret;
-	}
-	ret = ahci_probe_scsi(dev, base);
-	if (ret) {
-		debug("%s: Failed to probe (err=%d\n)", __func__, ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-static int sunxi_sata_bind(struct udevice *dev)
-{
-	struct udevice *scsi_dev;
-	int ret;
-
-	ret = ahci_bind_scsi(dev, &scsi_dev);
-	if (ret) {
-		debug("%s: Failed to bind (err=%d\n)", __func__, ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-static const struct udevice_id sunxi_ahci_ids[] = {
-	{ .compatible = "allwinner,sun4i-a10-ahci" },
-	{ }
-};
-
-U_BOOT_DRIVER(ahci_sunxi_drv) = {
-	.name		= "ahci_sunxi",
-	.id		= UCLASS_AHCI,
-	.of_match	= sunxi_ahci_ids,
-	.bind		= sunxi_sata_bind,
-	.probe		= sunxi_sata_probe,
-};
-#endif
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index 826650c89b..d8fdf7728e 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -12,14 +12,6 @@ void eth_init_board(void)
 	struct sunxi_ccm_reg *const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
-	/* Set up clock gating */
-#ifdef CONFIG_SUNXI_GEN_SUN6I
-	setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
-	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
-#else
-	setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
-#endif
-
 	/* Set MII clock */
 #ifdef CONFIG_RGMII
 	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |